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author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-30 17:37:28 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-09 17:22:24 +0000 |
commit | fc5b80943b849ae3f949c8647aca5bb91872e4a7 (patch) | |
tree | 832d3f18f7cc65fdbdeb5b465b4a83a3237c0b81 /src/arch/x86/mpspec.c | |
parent | 835ca8ee640c670f5e21ba30e4441c6526bdce12 (diff) | |
download | coreboot-fc5b80943b849ae3f949c8647aca5bb91872e4a7.tar.xz |
arch/x86/smbios: Add type 7
The SMBIOS spec requires type 7 to be present.
Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the
"Deterministic Cache Parameters" as available on Intel and AMD.
As CPUID only provides partial information on caches, some fields are set to
unknown.
The following fields are supported:
* Cache Level
* Cache Size
* Cache Type
* Cache Ways of Associativity
Tested on Intel Sandy Bridge (Lenovo T520).
All 4 caches are displayed in dmidecode and show the correct information.
Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/arch/x86/mpspec.c')
0 files changed, 0 insertions, 0 deletions