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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-31 11:53:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2016-08-01 21:40:23 +0200
commit049b46270d63c47db75b27246555c904e42fe9e2 (patch)
tree4b960b65f2309d8f979682d00e3b40ca1da1cc87 /src/arch/x86
parentf67e2cf9cf7a20e645ab2452c4b40e512bd21f50 (diff)
downloadcoreboot-049b46270d63c47db75b27246555c904e42fe9e2.tar.xz
arch/x86: Enable postcar console
Add a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/exit_car.S5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 421d5434a7..ca9b70e663 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -26,6 +26,11 @@ stack_top:
.text
.global _start
_start:
+#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE)
+ /* Enable the console */
+ call console_init
+#endif /* CONFIG_POSTCAR_CONSOLE */
+
/* chipset_teardown_car() is expected to disable cache-as-ram. */
call chipset_teardown_car