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authorAaron Durbin <adurbin@chromium.org>2016-04-29 12:10:28 -0500
committerAaron Durbin <adurbin@chromium.org>2016-05-02 20:04:56 +0200
commit800b0173c98101ee6ad2c7eaf1951a435c819fd9 (patch)
tree36c1b3b571030a50c543764f6610115d851788a0 /src/arch/x86
parenta6e9051bc6843bb8f42df9c29cd254914ece93b4 (diff)
downloadcoreboot-800b0173c98101ee6ad2c7eaf1951a435c819fd9.tar.xz
arch/x86/asembly_entry: reorder conditional stage entry macros
The path that just clears CAR_GLOBAL variables and jumps to the stage entry point needs another condition for separate verstage just after bootblock. However, the current conditional is a negative conditional so swap the logic around to make it easier to extend. Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14547 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/assembly_entry.S44
1 files changed, 23 insertions, 21 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 11babe1273..ec3888fa43 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -14,29 +14,9 @@
* GNU General Public License for more details.
*/
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
/*
- * The assembly.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/assembly.inc>
-
-#else
-/*
* This path is for stages that post bootblock when employing
* CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc
* as all those settings are cached within the processor. In order to
@@ -65,4 +45,26 @@ _start:
car_stage_entry:
1:
jmp 1b
+
+#else
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The assembly.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/assembly.inc>
+
#endif