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authorArthur Heymans <arthur@aheymans.xyz>2019-11-28 16:09:28 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-12-20 17:49:55 +0000
commit0e45b2875add588ddada7f40e294db99d62c3c3c (patch)
treebe6891cb3fc8d395e7662937d080aa8f3e89ef28 /src/arch/x86
parentba9b504ec5d8bc42f56cb085749c1296b1291ba9 (diff)
downloadcoreboot-0e45b2875add588ddada7f40e294db99d62c3c3c.tar.xz
arch/x86: Drop romcc bootblock
Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/Kconfig14
-rw-r--r--src/arch/x86/Makefile.inc57
-rw-r--r--src/arch/x86/bootblock.ld23
-rw-r--r--src/arch/x86/bootblock_normal.c66
-rw-r--r--src/arch/x86/bootblock_romcc.S49
-rw-r--r--src/arch/x86/bootblock_simple.c36
-rw-r--r--src/arch/x86/car.ld8
-rw-r--r--src/arch/x86/failover.ld66
-rw-r--r--src/arch/x86/include/arch/bootblock_romcc.h45
-rw-r--r--src/arch/x86/memlayout.ld1
10 files changed, 0 insertions, 365 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index a6f9f608a5..f4c0dc9e82 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -166,12 +166,6 @@ config BOOTBLOCK_DEBUG_SPINLOOP
Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
for a JTAG debugger to break into the execution sequence.
-config BOOTBLOCK_MAINBOARD_INIT
- string
-
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
-
config BOOTBLOCK_RESETS
string
@@ -184,9 +178,6 @@ config CMOS_DEFAULT_FILE
default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
depends on HAVE_CMOS_DEFAULT
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
-
config IOAPIC_INTERRUPTS_ON_FSB
bool
default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
@@ -256,11 +247,6 @@ config BOOTBLOCK_NORMAL
endchoice
-config BOOTBLOCK_SOURCE
- string
- default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
- default "bootblock_normal.c" if BOOTBLOCK_NORMAL
-
config SKIP_MAX_REBOOT_CNT_CLEAR
bool "Do not clear reboot count after successful boot"
depends on BOOTBLOCK_NORMAL
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f82148cf27..3b13efc46e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -116,8 +116,6 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-y += id.S
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
-
bootblock-y += bootblock_crt0.S
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
@@ -128,59 +126,6 @@ endif
bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
-else # ROMCC_BOOTBLOCK
-
-# x86-specific linker flags
-ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386
-else
-LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64
-endif
-
-# Add the assembly file that pulls in the rest of the dependencies in
-# the right order. Make sure the auto generated bootblock.inc is a proper
-# dependency. Make the same true for the linker sript.
-bootblock-y += bootblock_romcc.S
-bootblock-y += walkcbfs.S
-$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc
-
-bootblock-y += bootblock.ld
-$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld
-
-bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__
-ifeq ($(CONFIG_SSE),y)
-bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__
-endif
-
-# This is a hack in case there are no per chipset linker files.
-$(objgenerated)/empty: build-dirs
- touch $@
-
-$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
- @printf " GEN $(subst $(obj)/,,$(@))\n"
- cat $^ >> $@.tmp
- mv $@.tmp $@
-
--include $(objgenerated)/bootblock.inc.d
-$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
-# The open quote in the subst messes with syntax highlighting. Fix it - ")
- @printf " ROMCC $(subst $(obj)/,,$(@))\n"
- $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
- $< > $(objgenerated)/bootblock.inc.d
- $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \
- $< -o $(objgenerated)/bootblock_romcc.c
- $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
-
-# bootblock.ld is part of $(bootblock-objs)
-$(objcbfs)/bootblock.debug: $$(bootblock-objs)
- @printf " LINK $(subst $(obj)/,,$(@))\n"
- $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
- $(filter-out %.ld,$(bootblock-objs)) \
- -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld)
-
-endif # ROMCC_BOOTBLOCK
-
-
endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
###############################################################################
@@ -223,9 +168,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
# gdt_init.S is included by entry32.inc when romstage is the first C
# environment.
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
romstage-y += gdt_init.S
-endif
romstage-y += cbmem.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
deleted file mode 100644
index 10cd700322..0000000000
--- a/src/arch/x86/bootblock.ld
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/x86/failover.ld>
-#include <cpu/x86/16bit/entry16.ld>
-#include <cpu/x86/16bit/reset16.ld>
-#include <arch/x86/id.ld>
-#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
-#include <cpu/intel/fit/fit.ld>
-#endif
-
-/* Include generated .ld files. */
-#include <generated/bootblock.ld>
diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c
deleted file mode 100644
index 905ecb28fb..0000000000
--- a/src/arch/x86/bootblock_normal.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <smp/node.h>
-#include <arch/bootblock_romcc.h>
-#include <pc80/mc146818rtc.h>
-#include <halt.h>
-
-static const char *get_fallback(const char *stagelist)
-{
- while (*stagelist)
- stagelist++;
- return ++stagelist;
-}
-
-static void main(unsigned long bist)
-{
- u8 boot_mode;
- const char *default_filenames =
- "normal/romstage\0fallback/romstage";
-
- if (boot_cpu()) {
- bootblock_mainboard_init();
-
- sanitize_cmos();
-
- boot_mode = do_normal_boot();
- } else {
-
- /* Questionable single byte read from CMOS.
- * Do not add any other CMOS access in the
- * bootblock for AP CPUs.
- */
- boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE));
- }
-
- char *normal_candidate = (char *)walkcbfs("coreboot-stages");
-
- if (!normal_candidate)
- normal_candidate = default_filenames;
-
- unsigned long entry;
-
- if (boot_mode) {
- entry = findstage(normal_candidate);
- if (entry)
- call(entry, bist);
- }
-
- entry = findstage(get_fallback(normal_candidate));
- if (entry)
- call(entry, bist);
-
- /* duh. we're stuck */
- halt();
-}
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
deleted file mode 100644
index 7d6f42f08a..0000000000
--- a/src/arch/x86/bootblock_romcc.S
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * This is the original bootblock used by coreboot on x86 systems. It contains
- * a monolithic code flow, assembled from the following stages:
- * - reset16.inc: the reset vector
- * - entry16.inc: protected mode setup
- * - entry32.inc: segment descriptor setup
- * - timestamp.inc: store TSC in MMX registers
- * - generated/bootblock.inc: ROMCC part of the bootblock
- *
- * This is used on platforms which select ROMCC_BOOTBLOCK, and it
- * tries to do the absolute minimum before walking CBFS and jumping to romstage.
- *
- * This file assembles the bootblock program by the order of the includes. Thus,
- * it's extremely important that one pays very careful attention to the order
- * of the includes.
- */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/16bit/entry16.inc>
-#include <cpu/x86/16bit/reset16.inc>
-#include <cpu/x86/32bit/entry32.inc>
-
-#include <arch/x86/timestamp.inc>
-
-#if CONFIG(SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * This bootblock.inc file is generated by ROMCC. The above program flow
- * falls through to this point. ROMCC assumes the last function it parsed
- * is the main function and it places its instructions at the beginning of
- * the generated file. Moreover, any library/common code needed in bootblock
- * needs to come after bootblock.inc.
- */
-#include <generated/bootblock.inc>
diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
deleted file mode 100644
index d161435424..0000000000
--- a/src/arch/x86/bootblock_simple.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <smp/node.h>
-#include <arch/bootblock_romcc.h>
-#include <pc80/mc146818rtc.h>
-#include <halt.h>
-
-static void main(unsigned long bist)
-{
- if (boot_cpu()) {
- bootblock_mainboard_init();
-
- sanitize_cmos();
-#if CONFIG(CMOS_POST)
- cmos_post_init();
-#endif
- }
-
- const char *target1 = "fallback/romstage";
- unsigned long entry;
- entry = findstage(target1);
- if (entry)
- call(entry, bist);
- halt();
-}
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index d8ff4b36b7..2e29112467 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -36,11 +36,9 @@
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
-#if !CONFIG(ROMCC_BOOTBLOCK)
_car_stack = .;
. += CONFIG_DCACHE_BSP_STACK_SIZE;
_ecar_stack = .;
-#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that
* multiple stages (romstage and verstage) have a consistent
@@ -86,10 +84,6 @@
_ebss = .;
_car_unallocated_start = .;
-#if CONFIG(ROMCC_BOOTBLOCK)
- _car_stack = .;
- _ecar_stack = _car_region_end;
-#endif
_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
}
@@ -108,6 +102,4 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif
-#if !CONFIG(ROMCC_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
-#endif
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
deleted file mode 100644
index 139136540c..0000000000
--- a/src/arch/x86/failover.ld
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-ENTRY(_start)
-
-MEMORY {
- rom : ORIGIN = CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K
-}
-
-TARGET(binary)
-SECTIONS
-{
- /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
- * with Startup IPI message without RAM. Align .rom to next 4 byte
- * boundary anyway, so no pad byte appears between _rom and _start.
- */
- .bogus ROMLOC_MIN : {
- . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4);
- ROMLOC = .;
- } >rom = 0xff
-
- /* This section might be better named .setup */
- .rom ROMLOC : {
- _rom = .;
- *(.rom.text);
- *(.rom.data);
- *(.rom.data.*);
- *(.text);
- *(.text.*);
- *(.rodata);
- *(.rodata.*);
- _erom = .;
- } >rom = 0xff
-
- /* Allocation reserves extra 16 bytes here. Alignment requirements
- * may cause the total size of a section to change when the start
- * address gets applied.
- */
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
-
- /* Post-check proper SIPI vector. */
- _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff),
- "Address mismatch on AP_SIPI_VECTOR");
-
- /DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.eh_frame)
- *(.iplt)
- *(.rel.*)
- *(.igot.*)
- }
-}
diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h
deleted file mode 100644
index 827e40e985..0000000000
--- a/src/arch/x86/include/arch/bootblock_romcc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/lapic/boot_cpu.c>
-
-#ifdef CONFIG_BOOTBLOCK_RESETS
-#include CONFIG_BOOTBLOCK_RESETS
-#endif
-
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
-#include CONFIG_BOOTBLOCK_CPU_INIT
-#endif
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#endif
-
-#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
-#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
-#else
-static void bootblock_mainboard_init(void)
-{
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
- bootblock_northbridge_init();
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
- bootblock_southbridge_init();
-#endif
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
- bootblock_cpu_init();
-#endif
-}
-#endif
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index b14fd624a7..eff3738a43 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -49,7 +49,6 @@ SECTIONS
#include EARLY_MEMLAYOUT
#elif ENV_BOOTBLOCK
- /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */
BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
CONFIG_C_ENV_BOOTBLOCK_SIZE)