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authorAaron Durbin <adurbin@chromium.org>2015-09-29 16:31:20 -0500
committerAaron Durbin <adurbin@chromium.org>2015-10-14 17:07:52 +0000
commit75c51d9af15dfc599adaf7a8f6e892d452146f9c (patch)
treec4232740e4f08e94947dbe821bdccb0b43909b77 /src/arch/x86
parente3d2d6fd70ed932c98ac19f6294cb610d27fa7bf (diff)
downloadcoreboot-75c51d9af15dfc599adaf7a8f6e892d452146f9c.tar.xz
x86: add standalone verstage support
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/Makefile.inc34
-rw-r--r--src/arch/x86/bootblock_simple.c5
-rw-r--r--src/arch/x86/car.ld5
-rw-r--r--src/arch/x86/include/arch/early_variables.h17
-rw-r--r--src/arch/x86/include/arch/header.ld23
-rw-r--r--src/arch/x86/include/arch/memlayout.h4
-rw-r--r--src/arch/x86/memlayout.ld7
7 files changed, 88 insertions, 7 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 56b176d6b6..9b3101dc77 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -145,6 +145,9 @@ $(1)-y += memlayout.ld
$(1)-y += assembly_entry.S
$$(obj)/arch/x86/assembly_entry.$(1).o: $(objgenerated)/assembly.inc
+# The '.' include path is needed for the generated assembly.inc file.
+$(1)-S-ccopts += -I.
+
$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
@printf " LINK $$(subst $$(obj)/,,$$(@))\n"
$$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $$(obj)/arch/x86/memlayout.$(1).ld --oformat $(2)
@@ -157,6 +160,35 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
endef
###############################################################################
+# verstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
+
+verstage-y += boot.c
+
+verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
+verstage-y += memset.c
+verstage-y += memcpy.c
+verstage-y += memmove.c
+verstage-y += mmap_boot.c
+
+verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+verstage-libs += $(objgenerated)/libverstage.a
+
+ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y)
+$(eval $(call early_x86_stage,verstage,elf32-i386))
+else
+$(eval $(call early_x86_stage,verstage,elf64-x86-64))
+endif
+
+# Verstage on x86 expected to be xip.
+CBFSTOOL_VERSTAGE_OPTS = -a 64 --xip -S ".car.data"
+
+endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
+
+###############################################################################
# romstage
###############################################################################
@@ -211,7 +243,7 @@ $(eval $(call early_x86_stage,romstage,elf64-x86-64))
endif
# Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
-romstage-S-ccopts += -I. -g0
+romstage-S-ccopts += -g0
endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
index adeecf7ba6..bb0591fb53 100644
--- a/src/arch/x86/bootblock_simple.c
+++ b/src/arch/x86/bootblock_simple.c
@@ -15,7 +15,12 @@ static void main(unsigned long bist)
#endif
}
+#if CONFIG_SEPARATE_VERSTAGE
+ const char* target1 = "fallback/verstage";
+#else
const char* target1 = "fallback/romstage";
+#endif
+
unsigned long entry;
entry = findstage(target1);
if (entry) call(entry, bist);
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 5da9dcf32f..fa297162a0 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -22,6 +22,11 @@
/* This file is included inside a SECTIONS block */
. = CONFIG_DCACHE_RAM_BASE;
.car.data . (NOLOAD) : {
+ /* Vboot work buffer is completely volatile outside of verstage and
+ * romstage. Appropriate code needs to handle the transition. */
+#if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)
+ VBOOT2_WORK(., 16K)
+#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them at the beginning .car.data section
* so that multiple stages (romstage and verstage) have a consistent
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
index 7ccb340cf4..8a69fca9a0 100644
--- a/src/arch/x86/include/arch/early_variables.h
+++ b/src/arch/x86/include/arch/early_variables.h
@@ -21,6 +21,7 @@
#define ARCH_EARLY_VARIABLES_H
#include <stdlib.h>
+#include <rules.h>
#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM)
asm(".section .car.global_data,\"w\",@nobits");
@@ -31,11 +32,27 @@ asm(".previous");
#define CAR_GLOBAL __attribute__((used,section(".car.global_data#")))
#endif /* __clang__ */
+/*
+ * On x86 verstage, all CAR_GLOBAL variables are accessed unconditionally
+ * because cbmem is never initialized until romstage when dram comes up.
+ */
+#if ENV_VERSTAGE
+static inline void *car_get_var_ptr(void *var)
+{
+ return var;
+}
+
+static inline void *car_sync_var_ptr(void *var)
+{
+ return var;
+}
+#else
/* Get the correct pointer for the CAR global variable. */
void *car_get_var_ptr(void *var);
/* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/
void *car_sync_var_ptr(void *var);
+#endif /* ENV_VERSTAGE */
/* Get and set a primitive type global variable. */
#define car_get_var(var) \
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 0262c9208d..ca9b50a326 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -24,8 +24,23 @@ PHDRS
to_load PT_LOAD;
}
-#if ENV_RAMSTAGE || ENV_RMODULE
-ENTRY(_start)
-#elif ENV_ROMSTAGE
-ENTRY(protected_start)
+/*
+ * For CONFIG_SEPARATE_VERSTAGE romstage doesn't have the cache-as-ram setup.
+ * It only contains the teardown code. The verstage has the cache-as-ram setup
+ * code. Therefore, it needs the protected_start symbol as its entry point.
+ * The romstage entry will be named _start for consistency, but it's likely
+ * to be implemented in the chipset code in order to control the logic flow.
+ */
+#if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)
+ #if ENV_RAMSTAGE || ENV_RMODULE || ENV_ROMSTAGE
+ ENTRY(_start)
+ #elif ENV_VERSTAGE
+ ENTRY(protected_start)
+ #endif
+#else
+ #if ENV_RAMSTAGE || ENV_RMODULE
+ ENTRY(_start)
+ #elif ENV_ROMSTAGE
+ ENTRY(protected_start)
+ #endif
#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 91cfc8e064..18e10e2cf3 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -22,8 +22,8 @@
#include <rules.h>
-#if ENV_ROMSTAGE
-/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#if ENV_ROMSTAGE || ENV_VERSTAGE
+/* No .data or .bss sections. Cache as ram is handled separately. */
#define ARCH_STAGE_HAS_DATA_SECTION 0
#define ARCH_STAGE_HAS_BSS_SECTION 0
#endif
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 475f9bc912..f6a8dc0f19 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -39,5 +39,12 @@ SECTIONS
/* Pull in the cache-as-ram rules. */
#include "car.ld"
+#elif ENV_VERSTAGE
+ /* The 1M size is not allocated. It's just for basic size checking.
+ * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
+ VERSTAGE(32M, 1M)
+
+ /* Pull in the cache-as-ram rules. */
+ #include "car.ld"
#endif
}