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authorSiyuan Wang <wangsiyuanbuaa@gmail.com>2013-07-09 17:16:20 +0800
committerBruce Griffith <Bruce.Griffith@se-eng.com>2013-08-05 18:23:34 +0200
commit3e32cc00d1984e7a0d01039577e5aa6ae3b2aa81 (patch)
tree2c93698549d3d6e581ca0071739850fe5ccbf788 /src/arch/x86
parent5d7d09c4abfd60bebb7f17df3dce105fc22e9b92 (diff)
downloadcoreboot-3e32cc00d1984e7a0d01039577e5aa6ae3b2aa81.tar.xz
AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also changed because these two files depend on F16kb northbridge macros Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/boot/tables.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 3cc2c6b041..67d7911fe2 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -214,7 +214,7 @@ struct lb_memory *write_tables(void)
*/
cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
#endif
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
#endif
#endif