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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-05-02 16:30:53 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-03 20:33:42 +0200 |
| commit | 6870f0cc290c3aa106ccfc84ae62902b27eee4dc (patch) | |
| tree | 78cefb97ad6f7a8a7897b97ef38664ec4c8bd1ac /src/arch/x86 | |
| parent | f125d80135bad0f7736f20daae16073fff8e84f4 (diff) | |
| download | coreboot-6870f0cc290c3aa106ccfc84ae62902b27eee4dc.tar.xz | |
Make creation of CBMEM_ID_RESUME_SCRATCH depending on Agesa
The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one
particular board (AMD Persimmon). Make the creation of that section
depending on Agesa so it does consume space on non-Agesa systems.
Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/992
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/boot/tables.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 70f3117cb5..4fefc7d0d3 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -237,8 +237,10 @@ struct lb_memory *write_tables(void) * the result right now. If it fails, ACPI resume will be disabled. */ cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); +#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); #endif +#endif #if CONFIG_MULTIBOOT post_code(0x9d); |