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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-02-28 22:37:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-05 20:11:35 +0100 |
| commit | 73f7069fe6915cce545d4a5839ab1760e1fed2a2 (patch) | |
| tree | 164a29ca233f89e253aca08ee4b9407eaa17d684 /src/arch/x86 | |
| parent | dd56de974ddc7d0d8d782b50d9260b0596f59a1a (diff) | |
| download | coreboot-73f7069fe6915cce545d4a5839ab1760e1fed2a2.tar.xz | |
arch/x86: Add common assembly code for stages that run in CAR
This adds a few assembly lines that are generic enough to be shared
between romstage and verstage that are ran in CAR. The GDT reload
is bypassed and the stack is reloaded with the CAR stack defined
in car.ld. The entry point for all those stages is car_stage_entry().
Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/assembly_entry.S | 37 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 9 |
2 files changed, 45 insertions, 1 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 01e91b0f47..11babe1273 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. + * Copyright 2016 Google Inc. + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,8 @@ * GNU General Public License for more details. */ +#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) + /* This file assembles the start of the romstage program by the order of the * includes. Thus, it's extremely important that one pays very careful * attention to the order of the includes. */ @@ -31,3 +34,35 @@ * cache-as-ram setup files would be here. */ #include <generated/assembly.inc> + +#else +/* + * This path is for stages that post bootblock when employing + * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc + * as all those settings are cached within the processor. In order to + * continue with C code execution one needs to set stack pointer and clear + * CAR_GLOBAL variables that are stage specific. + */ +.section ".text._start", "ax", @progbits +.global _start +_start: + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + jmp car_stage_entry + +/* This is here for linking purposes. */ +.weak car_stage_entry +car_stage_entry: +1: + jmp 1b +#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 408fa15180..f50901fe73 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -239,4 +239,13 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) #define alwaysinline inline __attribute__((always_inline)) +#ifndef __ROMCC__ +/* + * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() + * is the symbol jumped to for each stage after bootblock using + * cache-as-ram. + */ +void asmlinkage car_stage_entry(void); +#endif + #endif /* ARCH_CPU_H */ |