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| author | Brenton Dong <brenton.m.dong@intel.com> | 2016-10-18 11:35:15 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-21 00:10:22 +0100 |
| commit | 0a5971c91bac57970e3f3229b8cda735a17b3a67 (patch) | |
| tree | bf8cf135b317da043224293efe07ec6971fe6010 /src/arch/x86 | |
| parent | f7acdf82cbfaf3e2b2b0db784b822207f1b1d026 (diff) | |
| download | coreboot-0a5971c91bac57970e3f3229b8cda735a17b3a67.tar.xz | |
drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown. Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/postcar.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index b6ae09a668..34a4335121 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -18,9 +18,14 @@ #include <main_decl.h> #include <program_loading.h> #include <soc/intel/common/util.h> +#include <fsp/util.h> void main(void) { + /* Call TempRamExit FSP API if enabled. */ + if (IS_ENABLED(CONFIG_FSP_CAR)) + fsp_temp_ram_exit(); + console_init(); /* Recover cbmem so infrastruture using it is functional. */ |