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| author | Marc Jones <marc.jones@se-eng.com> | 2012-11-02 14:26:44 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 05:39:19 +0100 |
| commit | 313ec9d15bb8c56fc76eb40be920552cb231465e (patch) | |
| tree | 5c409f649b1c478f1ed21795f6f0e152b0d4745d /src/arch/x86 | |
| parent | 7e8c8e92bb7c754a759b7f3bf955f6fd95d44d86 (diff) | |
| download | coreboot-313ec9d15bb8c56fc76eb40be920552cb231465e.tar.xz | |
Sandybridge: Set PEG clock gating
If the PEI System Agent doesn't run PCIe initialization, the PEG
clock gating will not be setup. Add the PEG clock gating when
pei_data->pcie_init is 0.
Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86')
0 files changed, 0 insertions, 0 deletions