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authorSiyuan Wang <wangsiyuanbuaa@gmail.com>2012-10-28 18:16:19 +0800
committerMarc Jones <marcj303@gmail.com>2012-11-07 02:03:36 +0100
commit6f05c2eb5963069977fcb4adce26ebbd5f1123bf (patch)
treee6ebe1d62d8af4435024784d817a652ee022eb18 /src/arch/x86
parentfa678bb87f2137d653dfd126da3d47902a048083 (diff)
downloadcoreboot-6f05c2eb5963069977fcb4adce26ebbd5f1123bf.tar.xz
AMD rd890 late.c: Don't enable PCIe ports after PCIe init.
PCIE devices are detected and initialized by the AMD PCIe init functions, which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init. Now, all bridges and devices are trained on the device 0.0 enable. After PCIe init, the PCIe ports with devices are on and the PCIe ports without devices are off. so resources may be allocated correctly during the rest of the PCI scan. But if the devicetree was being used to enable/disable devices after initialization, the problems would arise. Take a look at the serial log: do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges are still scanned. This is not correct. Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1640 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/arch/x86')
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