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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-27 19:02:55 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-08 15:19:09 +0200 |
| commit | e522258907c0f16fb46c8abfed64532fd3d81202 (patch) | |
| tree | 9107ba99f00c4e3b5dde029326b1707de11829df /src/arch/x86 | |
| parent | e223c3aee9ac7f3b91fbbb810e9f2b2acd3fc4f6 (diff) | |
| download | coreboot-e522258907c0f16fb46c8abfed64532fd3d81202.tar.xz | |
AGESA f14: Fix memory clock register decoding
Bottom five LSBs are used to store the running frequency
of memory clock.
Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19042
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch/x86')
0 files changed, 0 insertions, 0 deletions