summaryrefslogtreecommitdiff
path: root/src/arch/x86
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-03 10:51:34 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-11 01:29:35 +0200
commit33e5df3f25b4594c008788625cd405d988fc6e6b (patch)
treeddccf1263e8a71fe9d12202aa2a4c374c5a4e336 /src/arch/x86
parent52914323bf876342ab3497bfc527f139680d1612 (diff)
downloadcoreboot-33e5df3f25b4594c008788625cd405d988fc6e6b.tar.xz
Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/include/arch/pci_ops.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index e6027b7038..fa293173d5 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -22,8 +22,4 @@ static inline const struct pci_bus_operations *pci_config_default(void)
#endif
}
-static inline void pci_set_method(device_t dev)
-{
- dev->ops->ops_pci_bus = pci_config_default();
-}
#endif /* ARCH_I386_PCI_OPS_H */