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authorJulius Werner <jwerner@chromium.org>2020-04-21 16:03:53 -0700
committerJulius Werner <jwerner@chromium.org>2020-04-23 01:21:56 +0000
commit21a4053fde87801b42a0de39d5b6536c1ed4b475 (patch)
treea2cd4a48dbd4a2512c7e8e9c9e2a2b74e78aa98d /src/arch/x86
parentd9f26edfec760ff81f88f164fc0e601fe8e20e3e (diff)
downloadcoreboot-21a4053fde87801b42a0de39d5b6536c1ed4b475.tar.xz
rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/assembly_entry.S2
-rw-r--r--src/arch/x86/memlayout.ld2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index d48d28fbb0..f36e7dab4d 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -28,7 +28,7 @@ _start:
shrl $2, %ecx
rep stosl
-#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
+#if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
|| (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
/* Wait for a JTAG debugger to break in and set EBX non-zero */
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 05efac6db5..5e1ef24655 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -32,7 +32,7 @@ SECTIONS
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
#include EARLY_MEMLAYOUT
-#elif ENV_VERSTAGE
+#elif ENV_SEPARATE_VERSTAGE
/* The 1M size is not allocated. It's just for basic size checking.
* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)