Drop ROMCC code and header guards

Change-Id: I730f80afd8aad250f26534435aec24bea75a849c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

9 files changed, 4 insertions, 155 deletions

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 9d6f5a42b4..fef5ce9240 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -13,8 +13,6 @@
 
 #include <rules.h>
 
-#if !CONFIG(ROMCC_BOOTBLOCK)
-
 /*
  * This path is for stages that are post bootblock. The gdt is reloaded
  * to accommodate platforms that are executing out of CAR. In order to
@@ -60,26 +58,3 @@ debug_spinloop:
 	/* Expect to never return. */
 1:
 	jmp	1b
-
-#else
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if CONFIG(SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * The assembly.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/assembly.inc>
-
-#endif
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index bd99c21c91..887243964e 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -148,7 +148,7 @@ gdtaddr:
 	 .data
 
 	/* This is the gdt for GCC part of coreboot.
-	 * It is different from the gdt in ROMCC/ASM part of coreboot
+	 * It is different from the gdt in ASM part of coreboot
 	 * which is defined in entry32.inc
 	 *
 	 * When the machine is initially started, we use a very simple
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 479067ffaa..68475c157e 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -45,7 +45,7 @@
 #define ACPI_TABLE_CREATOR	"COREBOOT"  /* Must be exactly 8 bytes long! */
 #define OEM_ID			"COREv4"    /* Must be exactly 6 bytes long! */
 
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 #include <commonlib/helpers.h>
 #include <device/device.h>
 #include <uuid.h>
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 50d636b1f6..c8cf8c76c3 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -218,9 +218,6 @@ static inline bool cpu_is_intel(void)
 	return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON);
 }
 
-#ifndef __ROMCC__
-/* romcc does not support anonymous structs. */
-
 struct device;
 
 struct cpu_device_id {
@@ -288,13 +285,11 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 #define asmlinkage __attribute__((regparm(0)))
 
 /*
- * When not using a romcc bootblock the car_stage_entry() is the symbol
- * jumped to for each stage after bootblock using cache-as-ram.
+ * The car_stage_entry() is the symbol jumped to for each stage
+ * after bootblock using cache-as-ram.
  */
 asmlinkage void car_stage_entry(void);
 
-#endif
-
 /*
  * Get processor id using cpuid eax=1
  * return value in EAX register
diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h
index 7b18f55657..a3f5c853f3 100644
--- a/src/arch/x86/include/arch/hlt.h
+++ b/src/arch/x86/include/arch/hlt.h
@@ -14,16 +14,9 @@
 #ifndef ARCH_HLT_H
 #define ARCH_HLT_H
 
-#if defined(__ROMCC__)
-static void hlt(void)
-{
-	__builtin_hlt();
-}
-#else
 static __always_inline void hlt(void)
 {
 	asm("hlt");
 }
-#endif
 
 #endif /* ARCH_HLT_H */
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index d39bbb3ff4..43cfc1be12 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -21,39 +21,6 @@
  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
  * (insb/insw/insl/outsb/outsw/outsl).
  */
-#if defined(__ROMCC__)
-static inline void outb(uint8_t value, uint16_t port)
-{
-	__builtin_outb(value, port);
-}
-
-static inline void outw(uint16_t value, uint16_t port)
-{
-	__builtin_outw(value, port);
-}
-
-static inline void outl(uint32_t value, uint16_t port)
-{
-	__builtin_outl(value, port);
-}
-
-
-static inline uint8_t inb(uint16_t port)
-{
-	return __builtin_inb(port);
-}
-
-
-static inline uint16_t inw(uint16_t port)
-{
-	return __builtin_inw(port);
-}
-
-static inline uint32_t inl(uint16_t port)
-{
-	return __builtin_inl(port);
-}
-#else
 static inline void outb(uint8_t value, uint16_t port)
 {
 	__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
@@ -89,7 +56,6 @@ static inline uint32_t inl(uint16_t port)
 	__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
 	return value;
 }
-#endif /* __ROMCC__ */
 
 static inline void outsb(uint16_t port, const void *addr, unsigned long count)
 {
diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h
index f271a973eb..efdbe2752b 100644
--- a/src/arch/x86/include/arch/mmio.h
+++ b/src/arch/x86/include/arch/mmio.h
@@ -34,13 +34,11 @@ static __always_inline uint32_t read32(
 	return *((volatile uint32_t *)(addr));
 }
 
-#ifndef __ROMCC__
 static __always_inline uint64_t read64(
 	const volatile void *addr)
 {
 	return *((volatile uint64_t *)(addr));
 }
-#endif
 
 static __always_inline void write8(volatile void *addr,
 	uint8_t value)
@@ -60,12 +58,10 @@ static __always_inline void write32(volatile void *addr,
 	*((volatile uint32_t *)(addr)) = value;
 }
 
-#ifndef __ROMCC__
 static __always_inline void write64(volatile void *addr,
 	uint64_t value)
 {
 	*((volatile uint64_t *)(addr)) = value;
 }
-#endif
 
 #endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
deleted file mode 100644
index 36a88f1e4d..0000000000
--- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PCI_MMIO_CFG_ROMCC_H
-#define _PCI_MMIO_CFG_ROMCC_H
-
-#include <stdint.h>
-#include <device/mmio.h>
-#include <device/pci_type.h>
-
-
-static __always_inline
-uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
-{
-	void *addr;
-	addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
-	return read8(addr);
-}
-
-static __always_inline
-uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
-{
-	void *addr;
-	addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
-	return read16(addr);
-}
-
-static __always_inline
-uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
-{
-	void *addr;
-	addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
-	return read32(addr);
-}
-
-static __always_inline
-void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
-{
-	void *addr;
-	addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
-	write8(addr, value);
-}
-
-static __always_inline
-void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
-{
-	void *addr;
-	addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
-	write16(addr, value);
-}
-
-static __always_inline
-void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
-{
-	void *addr;
-	addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
-	write32(addr, value);
-}
-
-#endif /* _PCI_MMIO_CFG_ROMCC_H */
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index 4278ed0dfd..e706216586 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -15,12 +15,6 @@
 #define ARCH_I386_PCI_OPS_H
 
 #include <arch/pci_io_cfg.h>
-
-#if defined(__ROMCC__)
-/* Must come before <device/pci_mmio_cfg.h> */
-#include <arch/pci_mmio_cfg_romcc.h>
-#endif
-
 #include <device/pci_mmio_cfg.h>
 
 #endif /* ARCH_I386_PCI_OPS_H */