diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-05 21:22:02 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-05 22:47:13 +0200 |
| commit | 31324c64e12135f09590884421cbcbcabec1a62f (patch) | |
| tree | 912522f0cdd46f11b6fdb857b5c50eb583327d29 /src/arch/x86 | |
| parent | 8c5b58e7c372d0c1666931040e35fef92ad56c4b (diff) | |
| download | coreboot-31324c64e12135f09590884421cbcbcabec1a62f.tar.xz | |
Fill out ChromeOS specific coreboot table extensions
ChromeOS uses two extensions to the coreboot table:
- ChromeOS specific GPIO description for onboard switches
- position of verified boot area in nvram
Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/866
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/boot/coreboot_table.c | 43 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/coreboot_tables.h | 2 |
2 files changed, 45 insertions, 0 deletions
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index a9ff6f0f1b..219de7adae 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -179,6 +179,39 @@ static void lb_framebuffer(struct lb_header *header) #endif } +#if CONFIG_CHROMEOS +static void lb_gpios(struct lb_header *header) +{ + struct lb_gpios *gpios; + gpios = (struct lb_gpios *)lb_new_record(header); + gpios->tag = LB_TAG_GPIO; + gpios->size = sizeof(*gpios); + gpios->count = 0; + fill_lb_gpios(gpios); +} + +static void lb_vdat(struct lb_header *header) +{ + struct lb_vdat* vdat; + + vdat = (struct lb_vdat *)lb_new_record(header); + vdat->tag = LB_TAG_VDAT; + vdat->size = sizeof(*vdat); + acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); +} + +static void lb_vbnv(struct lb_header *header) +{ + struct lb_vbnv* vbnv; + + vbnv = (struct lb_vbnv *)lb_new_record(header); + vbnv->tag = LB_TAG_VBNV; + vbnv->size = sizeof(*vbnv); + vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; + vbnv->vbnv_size = CONFIG_VBNV_SIZE; +} +#endif + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -654,6 +687,16 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if CONFIG_CHROMEOS + /* Record our GPIO settings (ChromeOS specific) */ + lb_gpios(head); + + /* pass along the VDAT buffer adress */ + lb_vdat(head); + + /* pass along VBNV offsets in CMOS */ + lb_vbnv(head); +#endif add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h index 773e053835..b177949fb1 100644 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ b/src/arch/x86/include/arch/coreboot_tables.h @@ -20,4 +20,6 @@ struct lb_memory *get_lb_mem(void); int add_mainboard_resources(struct lb_memory *mem); int add_northbridge_resources(struct lb_memory *mem); +void fill_lb_gpios(struct lb_gpios *gpios); + #endif /* COREBOOT_TABLE_H */ |