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authorXiang Wang <wxjstz@126.com>2018-07-09 11:54:09 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-07-11 10:44:08 +0000
commit387417be03f9dcf9fe48fedd2e6ba6d356f51210 (patch)
treee21f913ada0d18eeb464da62b713fbc839bf9c43 /src/arch
parent654a45d2ad55fe6ea0a99fb98dcaeaf5a06a04be (diff)
downloadcoreboot-387417be03f9dcf9fe48fedd2e6ba6d356f51210.tar.xz
riscv: add support to check ISA extension
Add support to check ISA extension for RISC-V. Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/include/arch/cpu.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index a0ca3ce534..6008c75122 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -16,6 +16,8 @@
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__
+#include <arch/encoding.h>
+
#define asmlinkage
#if !defined(__PRE_RAM__)
@@ -44,5 +46,10 @@ struct cpuinfo_riscv {
#endif
+static inline int supports_extension(char ext)
+{
+ return read_csr(misa) & (1 << (ext - 'A'));
+}
+
struct cpu_info *cpu_info(void);
#endif /* __ARCH_CPU_H__ */