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| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-23 00:12:19 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-26 18:06:11 +0100 |
| commit | 5a767fdfcb08f0c23f6a9763a8f90a282de49326 (patch) | |
| tree | 4a00d548b2669e31c7b256e516d63c4aea5d33c0 /src/arch | |
| parent | 56075eaefcd7ef51464206166b24a0a47a59147f (diff) | |
| download | coreboot-5a767fdfcb08f0c23f6a9763a8f90a282de49326.tar.xz | |
x86: dynamic cbmem: fix acpi reservations
If a configuration was not using RELOCTABLE_RAMSTAGE, but it
was using HAVE_ACPI_RESUME then the ACPI memory was not being
marked as reserved to the OS. The reason is that memory is marked as
reserved during write_coreboot_table(). These reservations were
being added to cbmem after the call to write_coreboot_table(). In
the non-dynamic cbmem case this sequence is fine because cbmem area
is a fixed size and is already reserved. For the dynamic cbmem case
that no longer holds by the nature of the dynamic cbmem.
Change-Id: I9aa44205205bfef75a9e7d9f02cf5c93d7c457b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/boot/tables.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 4448333d61..6355a1b9dc 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -203,6 +203,22 @@ struct lb_memory *write_tables(void) } #endif + post_code(0x9e); + +#if CONFIG_HAVE_ACPI_RESUME +/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */ +#if !CONFIG_RELOCATABLE_RAMSTAGE + /* Let's prepare the ACPI S3 Resume area now already, so we can rely on + * it begin there during reboot time. We don't need the pointer, nor + * the result right now. If it fails, ACPI resume will be disabled. + */ + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); +#endif +#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); +#endif +#endif + #define MAX_COREBOOT_TABLE_SIZE (32 * 1024) post_code(0x9d); @@ -230,22 +246,6 @@ struct lb_memory *write_tables(void) rom_table_start, rom_table_end); } - post_code(0x9e); - -#if CONFIG_HAVE_ACPI_RESUME -/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */ -#if !CONFIG_RELOCATABLE_RAMSTAGE - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it begin there during reboot time. We don't need the pointer, nor - * the result right now. If it fails, ACPI resume will be disabled. - */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); -#endif -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); -#endif -#endif - #if CONFIG_MULTIBOOT post_code(0x9d); |