summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorDavid Hendricks <dhendrix@chromium.org>2013-04-07 17:26:34 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-04-08 18:31:08 +0200
commit6d0fe9cad003d752af3214ae9a91d7411d582950 (patch)
treea5c2c92fbe5d609c53ad37167ca7ae9d10dd3d5c /src/arch
parentc7e5d798420bb00f2c1853ca6abc11a7ee027886 (diff)
downloadcoreboot-6d0fe9cad003d752af3214ae9a91d7411d582950.tar.xz
armv7: specify condition code for msr instruction
This adds condition codes when using the msr instruction. Although described as "optional" in the Cortex-A series programmer's guide, our experience with using the msr instruction in the payload suggests that the condition code is not optional and that this only worked in coreboot (and u-boot) because the processor comes up in SVC32 mode. (credit to Gabe Black for finding this, I'm only uploading the patch) Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b Reviewed-on: http://review.coreboot.org/3037 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/armv7/bootblock.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
index c647834c5f..faf5475819 100644
--- a/src/arch/armv7/bootblock.inc
+++ b/src/arch/armv7/bootblock.inc
@@ -58,7 +58,7 @@ reset:
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
- msr cpsr,r0
+ msr cpsr_cxsf,r0
/*
* From Cortex-A Series Programmer's Guide: