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authorNikolay Petukhov <nikolay.petukhov@gmail.com>2008-03-29 16:59:27 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-03-29 16:59:27 +0000
commit9c2255c66c20cd90f39cc08c1220d93222d5d580 (patch)
tree5856ba073775b3259a454545d7b6a3fda4c82824 /src/arch
parent0e122af46553c394b1ac4c38dd83ab01c7c34a9c (diff)
downloadcoreboot-9c2255c66c20cd90f39cc08c1220d93222d5d580.tar.xz
Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/i386/boot/pirq_routing.c75
-rw-r--r--src/arch/i386/include/arch/pirq_routing.h6
2 files changed, 81 insertions, 0 deletions
diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c
index 62ba1a474e..fe4b0b47b4 100644
--- a/src/arch/i386/boot/pirq_routing.c
+++ b/src/arch/i386/boot/pirq_routing.c
@@ -1,6 +1,7 @@
#include <console/console.h>
#include <arch/pirq_routing.h>
#include <string.h>
+#include <device/pci.h>
#if (DEBUG==1 && HAVE_PIRQ_TABLE==1)
static void check_pirq_routing_table(struct irq_routing_table *rt)
@@ -94,6 +95,80 @@ unsigned long copy_pirq_routing_table(unsigned long addr)
memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size);
printk_info("done.\n");
verify_copy_pirq_routing_table(addr);
+ pirq_routing_irqs(addr);
return addr + intel_irq_routing_table.size;
}
#endif
+
+#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+void pirq_routing_irqs(unsigned long addr)
+{
+ int i, j, k, num_entries;
+ unsigned char irq_slot[4];
+ unsigned char pirq[4] = {0, 0, 0, 0};
+ struct irq_routing_table *pirq_tbl;
+ device_t pdev;
+
+ pirq_tbl = (struct irq_routing_table *)(addr);
+ num_entries = (pirq_tbl->size - 32) / 16;
+
+ /* Set PCI IRQs. */
+ for (i = 0; i < num_entries; i++) {
+
+ printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
+ pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot);
+
+ for (j = 0; j < 4; j++) {
+
+ int link = pirq_tbl->slots[i].irq[j].link;
+ int bitmap = pirq_tbl->slots[i].irq[j].bitmap & pirq_tbl->exclusive_irqs;
+ int irq = 0;
+
+ printk_debug("INT: %c link: %x bitmap: %x ",
+ 'A' + j, link, bitmap);
+
+ if (!bitmap|| !link || link > 4) {
+
+ printk_debug("not routed\n");
+ irq_slot[j] = irq;
+ continue;
+ }
+
+ /* yet not routed */
+ if (!pirq[link - 1]) {
+
+ for (k = 2; k < 15; k++) {
+
+ if (!((bitmap >> k) & 1))
+ continue;
+
+ irq = k;
+
+ /* yet not routed */
+ if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq)
+ break;
+ }
+
+ if (irq)
+ pirq[link - 1] = irq;
+ }
+ else
+ irq = pirq[link - 1];
+
+ printk_debug("IRQ: %d\n", irq);
+ irq_slot[j] = irq;
+ }
+
+ /* Bus, device, slots IRQs for {A,B,C,D}. */
+ pci_assign_irqs(pirq_tbl->slots[i].bus,
+ pirq_tbl->slots[i].devfn >> 3, irq_slot);
+ }
+
+ printk_debug("PIRQ1: %d\n", pirq[0]);
+ printk_debug("PIRQ2: %d\n", pirq[1]);
+ printk_debug("PIRQ3: %d\n", pirq[2]);
+ printk_debug("PIRQ4: %d\n", pirq[3]);
+
+ pirq_assign_irqs(pirq);
+}
+#endif
diff --git a/src/arch/i386/include/arch/pirq_routing.h b/src/arch/i386/include/arch/pirq_routing.h
index ef6fbeed0d..d3d61a282d 100644
--- a/src/arch/i386/include/arch/pirq_routing.h
+++ b/src/arch/i386/include/arch/pirq_routing.h
@@ -42,6 +42,12 @@ extern const struct irq_routing_table intel_irq_routing_table;
#if HAVE_PIRQ_TABLE==1
unsigned long copy_pirq_routing_table(unsigned long start);
unsigned long write_pirq_routing_table(unsigned long start);
+#if PIRQ_ROUTE==1
+void pirq_routing_irqs(unsigned long start);
+void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
+#else
+#define pirq_routing_irqs(start) {}
+#endif
#else
#define copy_pirq_routing_table(start) (start)
#define write_pirq_routing_table(start) (start)