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authorBrenton Dong <brenton.m.dong@intel.com>2016-10-18 13:57:54 -0700
committerMartin Roth <martinroth@google.com>2016-12-21 00:11:24 +0100
commitc9b398191e5f94647b3e4e80bafb5331ae49b7c8 (patch)
tree83c28799810ff66585bd26a9f21a0aaff6afa07e /src/arch
parent0a5971c91bac57970e3f3229b8cda735a17b3a67 (diff)
downloadcoreboot-c9b398191e5f94647b3e4e80bafb5331ae49b7c8.tar.xz
soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/exit_car.S5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 5c62c92af8..61287d2597 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -19,7 +19,8 @@
.section ".module_parameters", "aw", @progbits
/* stack_top indicates the stack to pull MTRR information from. */
-stack_top:
+.global post_car_stack_top
+post_car_stack_top:
.long 0
.long 0
@@ -38,7 +39,7 @@ _start:
invd
/* Set up new stack. */
- mov stack_top, %esp
+ mov post_car_stack_top, %esp
/*
* Honor variable MTRR information pushed on the stack with the