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authorDuncan Laurie <dlaurie@chromium.org>2013-06-10 09:53:33 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-26 19:08:48 +0100
commite807c34a5e34e8dd7cb959458de593ea1070fde4 (patch)
tree5b7ea1d5fb675add375221c745c585e9f6484a26 /src/arch
parent35bd3fedfeafe96b5fb938c1b47e2b0380fdbfb7 (diff)
downloadcoreboot-e807c34a5e34e8dd7cb959458de593ea1070fde4.tar.xz
cmos post: Guard with spinlock
The CMOS post code storage mechanism does back-to-back CMOS reads and writes that may be interleaved during CPU bringup, leading to corruption of the log or of other parts of CMOS. Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58102 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/include/arch/smp/spinlock.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 5c1dd94c36..32be2f25fb 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -1,6 +1,8 @@
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H
+#ifndef __PRE_RAM__
+
/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
*/
@@ -61,4 +63,16 @@ static inline __attribute__((always_inline)) void cpu_relax(void)
__asm__ __volatile__("rep;nop": : :"memory");
}
+#else /* !__PRE_RAM__ */
+
+#define DECLARE_SPIN_LOCK(x)
+#define barrier() do {} while(0)
+#define spin_is_locked(lock) 0
+#define spin_unlock_wait(lock) do {} while(0)
+#define spin_lock(lock) do {} while(0)
+#define spin_unlock(lock) do {} while(0)
+#define cpu_relax() do {} while(0)
+
+#endif /* !__PRE_RAM__ */
+
#endif /* ARCH_SMP_SPINLOCK_H */