device/pci_ops: Have only default PCI bus ops available

In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.

This change effectively inlines all PCI config accessors
for ramstage as well.

Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 0 insertions, 60 deletions

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index e3151ef1a9..6e4ee76c55 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -327,8 +327,6 @@ ramstage-y += memmove.c
 ramstage-y += memset.c
 ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
-ramstage-y += pci_ops_conf1.c
-ramstage-$(CONFIG_NO_MMCONF_SUPPORT) += pci_ops.c
 ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
 ramstage-y += rdrand.c
 ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index 67633f43e9..e706216586 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -17,10 +17,4 @@
 #include <arch/pci_io_cfg.h>
 #include <device/pci_mmio_cfg.h>
 
-#ifndef __SIMPLE_DEVICE__
-
-extern const struct pci_bus_operations pci_cf8_conf1;
-
-#endif
-
 #endif /* ARCH_I386_PCI_OPS_H */
diff --git a/src/arch/x86/pci_ops.c b/src/arch/x86/pci_ops.c
deleted file mode 100644
index f30bffe320..0000000000
--- a/src/arch/x86/pci_ops.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2018 Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci_ops.h>
-
-const struct pci_bus_operations *pci_bus_default_ops(void)
-{
-	return &pci_cf8_conf1;
-}
diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c
deleted file mode 100644
index 03c2b64183..0000000000
--- a/src/arch/x86/pci_ops_conf1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <arch/pci_io_cfg.h>
-
-/*
- * Functions for accessing PCI configuration space with type 1 accesses
- */
-
-const struct pci_bus_operations pci_cf8_conf1 = {
-	.read8 = pci_io_read_config8,
-	.read16 = pci_io_read_config16,
-	.read32 = pci_io_read_config32,
-	.write8 = pci_io_write_config8,
-	.write16 = pci_io_write_config16,
-	.write32 = pci_io_write_config32,
-};