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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-22 13:00:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-26 10:20:09 +0000 |
| commit | 5fd50b6b198d7e086945ca0255ccc0757b31f748 (patch) | |
| tree | 7cbbe92d78396d36e8d433dce9a8408cc8eb22af /src/arch | |
| parent | 098240eb4fd4ef59510d5138538f2a2f7cc5dcdc (diff) | |
| download | coreboot-5fd50b6b198d7e086945ca0255ccc0757b31f748.tar.xz | |
nb/intel/sandybridge: Add and use TC_DTP definition
This register is specific to Ivy Bridge. This changes the binary because
the operations get reordered, but it is equivalent.
Change-Id: Ibc9127e0fc268466c13f7c5ac8d942543713ca32
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions