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authorFurquan Shaikh <furquan@google.com>2014-10-02 16:43:19 -0700
committerAaron Durbin <adurbin@google.com>2015-04-07 18:06:28 +0200
commit6f33f0a87d7ce60d10d2fe9cfa3f721fb598840e (patch)
treee5e26c423275056be14b88da21780ec4b0fa5c58 /src/arch
parenta48ca841a2f2a24d53cc47d54453d60d15cbfadc (diff)
downloadcoreboot-6f33f0a87d7ce60d10d2fe9cfa3f721fb598840e.tar.xz
arm64: Add verstage support
This stage is not tested on any hardware. BUG=None BRANCH=None TEST=Compiles successfully for rush_ryu and veyron_pinky Original-Change-Id: I6dd266471c815895bb3dd53d34aacc8fe825eeb6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221911 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 907ea2d1f8c9f01d815e8673695dd5271322c7a8) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I617a742d4a387be947086dae33e9a913f742a8d1 Reviewed-on: http://review.coreboot.org/9255 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm64/Makefile.inc20
-rw-r--r--src/arch/arm64/armv8/Makefile.inc14
-rw-r--r--src/arch/arm64/armv8/lib/Makefile.inc4
3 files changed, 38 insertions, 0 deletions
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index b2b627c07f..1bc6c1113e 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -76,6 +76,26 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
endif # CONFIG_ARCH_BOOTBLOCK_ARM64
+###############################################################################
+# verification stage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
+
+$(objcbfs)/verstage.debug: $$(verstage-objs) $$(VB2_LIB) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(verstage-objs) $(VBS_LIB) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+
+verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
+verstage-y += div0.c
+verstage-y += eabi_compat.c
+verstage-y += ../../lib/memset.c
+verstage-y += ../../lib/memcpy.c
+verstage-y += ../../lib/memmove.c
+verstage-y += stages.c
+
+endif # CONFIG_ARCH_VERSTAGE_ARM64
+
################################################################################
# romstage
################################################################################
diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc
index ae9f38dd75..5532b47a14 100644
--- a/src/arch/arm64/armv8/Makefile.inc
+++ b/src/arch/arm64/armv8/Makefile.inc
@@ -46,6 +46,20 @@ bootblock-S-ccopts += $(armv8_asm_flags)
endif
################################################################################
+## verstage
+################################################################################
+ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y)
+
+verstage-y += cache.c
+verstage-y += cpu.S
+verstage-y += exception.c
+
+verstage-c-ccopts += $(armv8_flags)
+verstage-S-ccopts += $(armv8_asm_flags)
+
+endif
+
+################################################################################
## romstage
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y)
diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc
index 0622593e4f..7e647bd6bc 100644
--- a/src/arch/arm64/armv8/lib/Makefile.inc
+++ b/src/arch/arm64/armv8/lib/Makefile.inc
@@ -26,6 +26,10 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y)
bootblock-y += $(lib_access)
endif
+ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y)
+verstage-y += $(lib_access)
+endif
+
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y)
romstage-y += $(lib_access)
endif