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| author | Julius Werner <jwerner@chromium.org> | 2020-12-30 15:51:10 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-19 08:39:26 +0000 |
| commit | 82d16b150ce3287f4e9f33e86bdde32bc455b193 (patch) | |
| tree | f3110d34e3eebb4a57ca429152c1262e65e9f2f4 /src/arch | |
| parent | 422501fb14780090527c9a45bcca6628cd6bba71 (diff) | |
| download | coreboot-82d16b150ce3287f4e9f33e86bdde32bc455b193.tar.xz | |
memlayout: Store region sizes as separate symbols
This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/c_start.S | 2 | ||||
| -rw-r--r-- | src/arch/x86/car.ld | 17 |
2 files changed, 7 insertions, 12 deletions
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 8bebf87435..19532d82dc 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -8,6 +8,7 @@ .section .bss, "aw", @nobits .global _stack .global _estack +.global _stack_size /* Stack alignment is not enforced with rmodule loader, reserve one * extra CPU such that alignment can be enforced on entry. */ @@ -15,6 +16,7 @@ _stack: .space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE _estack: +.set _stack_size, _estack - _stack #if CONFIG(COOP_MULTITASKING) .global thread_stacks thread_stacks: diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5207157fe9..5a46b8b2ec 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -11,9 +11,7 @@ #if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ - _pagetables = . ; - . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; - _epagetables = . ; + REGION(pagetables, ., 4K * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4K) #endif #if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* Vboot work buffer only needs to be available when verified boot @@ -28,9 +26,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ - _car_stack = .; - . += CONFIG_DCACHE_BSP_STACK_SIZE; - _ecar_stack = .; + REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 4) /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that * multiple stages (romstage and verstage) have a consistent @@ -42,9 +38,7 @@ * totalling 32 bytes that need to be 32-byte aligned. The reason the * pdpt are not colocated with the rest of the page tables is to reduce * fragmentation of the CAR space that persists across stages. */ - _pdpt = .; - . += 32; - _epdpt = .; + REGION(pdpt, ., 32, 32) #endif TIMESTAMP(., 0x200) @@ -56,10 +50,8 @@ FMAP_CACHE(., FMAP_SIZE) #endif - _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ - . += 80; - _ecar_ehci_dbg_info = .; + REGION(car_ehci_dbg_info, ., 80, 1) /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -75,6 +67,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; + RECORD_SIZE(bss) #if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; |