diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2013-07-08 18:41:02 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-12-12 22:06:08 +0100 |
| commit | c5aac958ae99bd556d077a49618e4a5daf0e65f3 (patch) | |
| tree | e072d39d7591269ae8de0026bd65b9f74c7509d4 /src/arch | |
| parent | 356833d0b5379de6d960b479b6a9eb7d6b971b86 (diff) | |
| download | coreboot-c5aac958ae99bd556d077a49618e4a5daf0e65f3.tar.xz | |
exynos5250: Correct DDR3 Phy-reset value names.
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".
To prevent confusion, we should rename the constants to "RESET_ENABLE" and
"RESET_DISABLE".
Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
Reviewed-on: https://gerrit.chromium.org/gerrit/61081
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4357
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions