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authorXiang Wang <wxjstz@126.com>2018-07-20 16:16:46 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-08-01 14:37:06 +0000
commit07bc3251a9c74ecb4f96878b99e3537307c6c685 (patch)
tree4079f16b3e9c73241a892b831634853e9a57d709 /src/arch
parentee09878f4520e04547757d5af9e597d44f9c82db (diff)
downloadcoreboot-07bc3251a9c74ecb4f96878b99e3537307c6c685.tar.xz
riscv: remove redundancy in Makefile
src/arch/riscv/stages.c is an entry of romstage/ramstage, and does not needs to be bootblock. src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some compile/board/time information, which is repeated with src/lib/version.c Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27557 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/Makefile.inc5
-rw-r--r--src/arch/riscv/id.S33
-rw-r--r--src/arch/riscv/id.ld19
3 files changed, 1 insertions, 56 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 85bec43c50..c4859408f3 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -40,10 +40,7 @@ COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-fi
################################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
-bootblock-y += id.S
-$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
-
-bootblock-y = bootblock.S stages.c
+bootblock-y = bootblock.S
bootblock-y += trap_util.S
bootblock-y += trap_handler.c
bootblock-y += mcall.c
diff --git a/src/arch/riscv/id.S b/src/arch/riscv/id.S
deleted file mode 100644
index 311b989aed..0000000000
--- a/src/arch/riscv/id.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <build.h>
-
- .section ".id", "a", %progbits
-
- .globl __id_start
-__id_start:
-ver:
- .asciz COREBOOT_VERSION
-vendor:
- .asciz CONFIG_MAINBOARD_VENDOR
-part:
- .asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
-.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
-.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE /* Size of this romimage */
- .globl __id_end
-
-__id_end:
-.previous
diff --git a/src/arch/riscv/id.ld b/src/arch/riscv/id.ld
deleted file mode 100644
index 932375665e..0000000000
--- a/src/arch/riscv/id.ld
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-SECTIONS {
- . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
- .id (.): {
- *(.id)
- }
-}