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authorAaron Durbin <adurbin@chromium.org>2016-07-13 23:13:25 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:31:21 +0200
commit20a588b3de9671f8166be4c94271e79966fc559b (patch)
tree0e02a3d12f5f27658c07e76e2de8967707ccd597 /src/arch
parent932e09d168ba180ee0a17319c1e9cd73009a7adb (diff)
downloadcoreboot-20a588b3de9671f8166be4c94271e79966fc559b.tar.xz
arch/x86: provide common Intel ACPI hardware definitions
In the ACPI specification the PM1 register locations are well defined, but the sleep type values are hardware specific. That said, the Intel chipsets have been consistent with the values they use. Therefore, provide those hardware definitions as well a helper function for translating the hardware values to the more high level ACPI sleep values. BUG=chrome-os-partner:54977 Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/include/arch/acpi.h34
1 files changed, 32 insertions, 2 deletions
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 03cd70948e..dfbffb3ab7 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -31,7 +31,22 @@
#define HIGH_MEMORY_SAVE 0
#endif
-#ifndef __ASSEMBLER__
+#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+/*
+ * The type and enable fields are common in ACPI, but the
+ * values themselves are hardware implementation idefiend.
+ */
+#define SLP_EN (1 << 13)
+#define SLP_TYP_SHIFT 10
+#define SLP_TYP (7 << SLP_TYP_SHIFT)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
#include <stdint.h>
#include <rules.h>
#include <commonlib/helpers.h>
@@ -624,6 +639,21 @@ enum {
ACPI_S5,
};
+#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+/* Given the provided PM1 control register return the ACPI sleep type. */
+static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
+{
+ switch (((pm1_cnt) & SLP_TYP) >> SLP_TYP_SHIFT) {
+ case SLP_TYP_S0: return ACPI_S0;
+ case SLP_TYP_S1: return ACPI_S1;
+ case SLP_TYP_S3: return ACPI_S3;
+ case SLP_TYP_S4: return ACPI_S4;
+ case SLP_TYP_S5: return ACPI_S5;
+ }
+ return -1;
+}
+#endif
+
/* Returns ACPI_Sx values. */
int acpi_get_sleep_type(void);
@@ -660,6 +690,6 @@ static inline uintptr_t acpi_align_current(uintptr_t current)
return ALIGN(current, 16);
}
-#endif /* __ASSEMBLER__ */
+#endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__)
#endif /* __ASM_ACPI_H */