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authorStefan Reinauer <reinauer@chromium.org>2011-11-17 13:05:31 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-30 17:45:53 +0200
commit5e02bc6d7ef7f976629a7bfb35429527a77e6321 (patch)
tree718892e572b79c5a1c4b87d959ca2649161baec7 /src/arch
parentbf729baa2c7b2fbfa03e271c4f3f5707989e43b5 (diff)
downloadcoreboot-5e02bc6d7ef7f976629a7bfb35429527a77e6321.tar.xz
Make PCI CONF2 support a compile time option
It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/758 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/Kconfig4
-rw-r--r--src/arch/x86/lib/Makefile.inc4
-rw-r--r--src/arch/x86/lib/pci_ops_auto.c9
3 files changed, 13 insertions, 4 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 4ca49cbaf4..f49d09b872 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -100,4 +100,8 @@ config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
bool
default n
+config PCI_CONF2
+ bool
+ default n
+
endmenu
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3f4dc95560..96fb9b07f5 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -1,10 +1,8 @@
ramstage-y += c_start.S
ramstage-y += cpu.c
ramstage-y += pci_ops_conf1.c
-ramstage-y += pci_ops_conf2.c
-
+ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
-
ramstage-y += pci_ops_auto.c
ramstage-y += exception.c
ramstage-$(CONFIG_IOAPIC) += ioapic.c
diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c
index 92eedd30fb..58e098b655 100644
--- a/src/arch/x86/lib/pci_ops_auto.c
+++ b/src/arch/x86/lib/pci_ops_auto.c
@@ -6,6 +6,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#if CONFIG_PCI_CONF2
/*
* Before we decide to use direct hardware access mechanisms, we try to do some
* trivial checks to ensure it at least _seems_ to be working -- we just test
@@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o)
return 0;
}
-struct pci_bus_operations *pci_bus_fallback_ops = NULL;
+static struct pci_bus_operations *pci_bus_fallback_ops = NULL;
static const struct pci_bus_operations *pci_check_direct(void)
{
@@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void)
pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct();
return pci_bus_fallback_ops;
}
+#else
+const struct pci_bus_operations *pci_remember_direct(void)
+{
+ return &pci_cf8_conf1;
+}
+#endif
/** Set the method to be used for PCI, type I or type II
*/