summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorXiang Wang <wxjstz@126.com>2018-07-12 14:56:05 +0800
committerMartin Roth <martinroth@google.com>2018-07-17 18:09:43 +0000
commit5fed693a52ed9746900ce58ec12a2b245f08202e (patch)
tree29bc3c68250a8365e0c25134f4383b07d29bb93f /src/arch
parent745e58a5ee50373276924349524a2594599e8bb5 (diff)
downloadcoreboot-5fed693a52ed9746900ce58ec12a2b245f08202e.tar.xz
riscv: add support for modifying compiler options
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/Kconfig14
-rw-r--r--src/arch/riscv/Makefile.inc12
2 files changed, 14 insertions, 12 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 2513c50030..916e269b32 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -2,12 +2,14 @@ config ARCH_RISCV
bool
default n
-config ARCH_RISCV_COMPRESSED
- bool
- default n
- help
- Enable this option if your RISC-V processor supports compressed
- instructions (RVC). Currently, this enables RVC for all stages.
+config RISCV_ARCH
+ string
+
+config RISCV_ABI
+ string
+
+config RISCV_CODEMODEL
+ string
config ARCH_BOOTBLOCK_RISCV
bool
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 4b2ff035d7..90e4240468 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -23,15 +23,15 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
check-ramstage-overlap-regions += stack
endif
-riscv_arch = rv64imafd
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
-ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
- riscv_arch := $(riscv_arch)c
-endif
+riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
+
+COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
+COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
-riscv_asm_flags = -march=$(riscv_arch)
+COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
################################################################################
## bootblock