summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-04-19 07:37:38 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-05-18 06:47:34 +0200
commita7dd6455942e17708d5d8da3e1f6c22a8f75ac2e (patch)
tree3854da0d24ebe6b54f69f1d32baaef4b1cf655ce /src/arch
parentae6a4b6d3ca60fc697103cbdaaf5df84502f554e (diff)
downloadcoreboot-a7dd6455942e17708d5d8da3e1f6c22a8f75ac2e.tar.xz
CBMEM: Add config CBMEM_TOP_BACKUP
AGESA and binaryPI boards have no easy way to determine correct cbmem_top() location early enough when GFXUMA is enabled, so they will use these functions with EARLY_CBMEM_INIT as well. At the end of AmdInitPost() the decisions of UMA base and size have not been written to hardware yet. The decisions are stored inside AGESA heap object we cannot locate from coreboot proper until after AmdInitEnv(). Modify code such that weak backup functions are only defined for LATE_CBMEM_INIT; they are somewhat troublesome to handle. Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19306 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/Kconfig7
-rw-r--r--src/arch/x86/cbmem.c44
2 files changed, 28 insertions, 23 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 0c8b97d2f3..e18d6d05dd 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -111,8 +111,15 @@ config ROMCC
bool
default n
+config CBMEM_TOP_BACKUP
+ def_bool n
+ help
+ Platform implements non-volatile storage to cache cbmem_top()
+ over stage transitions and optionally also over S3 suspend.
+
config LATE_CBMEM_INIT
def_bool n
+ select CBMEM_TOP_BACKUP
help
Enable this in chipset's Kconfig if northbridge does not implement
early get_top_of_ram() call for romstage. CBMEM tables will be
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 578bb8a4ed..e35d43cecb 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -18,49 +18,47 @@
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-#if !defined(__PRE_RAM__)
void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
{
/* Do nothing. Chipset may have implementation to save ramtop in NVRAM.
*/
}
-static void *ramtop_pointer;
-
-void set_top_of_ram(uint64_t ramtop)
+unsigned long __attribute__((weak)) get_top_of_ram(void)
{
- backup_top_of_ram(ramtop);
- ramtop_pointer = (void *)(uintptr_t)ramtop;
+ return 0;
}
-static inline void *saved_ramtop(void)
-{
- return ramtop_pointer;
-}
-#else
-static inline void *saved_ramtop(void)
-{
- return NULL;
-}
-#endif /* !__PRE_RAM__ */
+#endif /* LATE_CBMEM_INIT */
-unsigned long __attribute__((weak)) get_top_of_ram(void)
+#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)
+
+static void *ramtop_pointer;
+
+void set_top_of_ram(uint64_t ramtop)
{
- return 0;
+ backup_top_of_ram(ramtop);
+ if (ENV_RAMSTAGE)
+ ramtop_pointer = (void *)(uintptr_t)ramtop;
}
void *cbmem_top(void)
{
/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
- void *ptr = saved_ramtop();
+ uintptr_t ramtop;
+
+ if (ENV_RAMSTAGE && ramtop_pointer != NULL)
+ return ramtop_pointer;
- if (ptr != NULL)
- return ptr;
+ ramtop = get_top_of_ram();
- return (void *)get_top_of_ram();
+ if (ENV_RAMSTAGE)
+ ramtop_pointer = (void *)ramtop;
+
+ return (void *)ramtop;
}
-#endif /* LATE_CBMEM_INIT */
+#endif /* CBMEM_TOP_BACKUP */
/* Something went wrong, our high memory area got wiped */
void cbmem_fail_resume(void)