summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-02-28 14:01:34 +0200
committerMarc Jones <marcj303@gmail.com>2012-04-02 21:13:26 +0200
commitabdf15f40b1e0838a43a54704ba5277c8210d69f (patch)
tree0dcf0ca40cc6a85df79fabaaab8748e59a018ad7 /src/arch
parentafd141d5043b4e1489c4e4796fc50c43ef9b23e2 (diff)
downloadcoreboot-abdf15f40b1e0838a43a54704ba5277c8210d69f.tar.xz
Apply cache-as-ram conditionally on socket mPGA604
The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/607 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
-rwxr-xr-xsrc/arch/x86/Makefile.inc8
1 files changed, 1 insertions, 7 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 00e7b86225..8783d4bc02 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -193,13 +193,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc
endif
crt0s += $(cpu_incs)
-
-#
-# FIXME move to CPU_INTEL_SOCKET_MPGA604
-#
-ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
-crt0s += $(src)/cpu/intel/car/cache_as_ram.inc
-endif
+crt0s += $(cpu_incs-y)
ifeq ($(CONFIG_LLSHELL),y)
crt0s += $(src)/arch/x86/llshell/llshell.inc