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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-08-22 19:37:15 +0200
committerMartin Roth <martinroth@google.com>2016-08-23 16:05:16 +0200
commitd9ff75f2cb944d3536f7a502c1c7519843c06618 (patch)
tree55c4bcadd619416cc8d5559f2865b8b74203f933 /src/arch
parent538e44683bd51f619214f87d8321a0e62cd7e358 (diff)
downloadcoreboot-d9ff75f2cb944d3536f7a502c1c7519843c06618.tar.xz
arch/riscv: Delegate exceptions to supervisor mode if appropriate
Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16160 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/virtual_memory.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index bea552de86..98b7edca4e 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -208,4 +208,14 @@ void mstatus_init(void)
clear_csr(mip, MIP_MSIP);
set_csr(mie, MIP_MSIP);
+
+ /* Configure which exception causes are delegated to supervisor mode */
+ set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH)
+ | (1 << CAUSE_FAULT_FETCH)
+ | (1 << CAUSE_ILLEGAL_INSTRUCTION)
+ | (1 << CAUSE_BREAKPOINT)
+ | (1 << CAUSE_FAULT_LOAD)
+ | (1 << CAUSE_FAULT_STORE)
+ | (1 << CAUSE_USER_ECALL)
+ );
}