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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-31 14:52:20 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-03 06:15:35 +0000
commit0d6ddf8da7632e775dde92c9114ac6ace5ca5f14 (patch)
tree67b37afc2c6bc3cfaa3750a87394c5b056067137 /src/arch
parentea2bec2c4b1a986b059147506c99a202d5c8fad3 (diff)
downloadcoreboot-0d6ddf8da7632e775dde92c9114ac6ace5ca5f14.tar.xz
cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/cpu.c2
-rw-r--r--src/arch/x86/timestamp.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index cfab21956b..30d2cca87a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -315,7 +315,7 @@ void lb_arch_add_records(struct lb_header *header)
struct lb_tsc_info *tsc_info;
/* Don't advertise a TSC rate unless it's constant. */
- if (!CONFIG(TSC_CONSTANT_RATE))
+ if (!tsc_constant_rate())
return;
freq_khz = tsc_freq_mhz() * 1000;
diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c
index 92d9590af4..8cf0f96e31 100644
--- a/src/arch/x86/timestamp.c
+++ b/src/arch/x86/timestamp.c
@@ -22,7 +22,7 @@ uint64_t timestamp_get(void)
int timestamp_tick_freq_mhz(void)
{
/* Chipsets that have a constant TSC provide this value correctly. */
- if (CONFIG(TSC_CONSTANT_RATE))
+ if (tsc_constant_rate())
return tsc_freq_mhz();
/* Filling tick_freq_mhz = 0 in timestamps-table will trigger