diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-09-06 02:40:54 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:05:22 +0100 |
| commit | 3693838d47a133cc0133353ea6361e6fef8b664d (patch) | |
| tree | 2997bb171770728f139ae46272a92b75125b1569 /src/arch | |
| parent | b6a81fa94b93319288bd2f3300889a651cab91b4 (diff) | |
| download | coreboot-3693838d47a133cc0133353ea6361e6fef8b664d.tar.xz | |
arm64: remove soc_secondary_cpu_init()
The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e
Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216927
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm64/c_entry.c | 14 | ||||
| -rw-r--r-- | src/arch/arm64/cpu-internal.h | 7 | ||||
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/cpu.h | 13 |
3 files changed, 7 insertions, 27 deletions
diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index aba9fd3719..4e5c1510c0 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -36,11 +36,6 @@ void __attribute__((weak)) arm64_soc_init(void) /* Default weak implementation does nothing. */ } -void __attribute__((weak)) soc_secondary_cpu_init(void) -{ - /* Default weak implementation does nothing. */ -} - static void seed_stack(void) { char *stack_begin; @@ -71,15 +66,6 @@ static void secondary_cpu_start(void) mmu_enable(); exception_hwinit(); - if (!IS_ENABLED(CONFIG_SMP)) { - soc_secondary_cpu_init(); - /* - * TODO(adurbin): need a proper place to park the CPUs. - * Currently assuming SoC code does the appropriate thing. - */ - while (1); - } - /* This will never return. */ arch_secondary_cpu_init(); } diff --git a/src/arch/arm64/cpu-internal.h b/src/arch/arm64/cpu-internal.h index be13ba4e98..266dc633c6 100644 --- a/src/arch/arm64/cpu-internal.h +++ b/src/arch/arm64/cpu-internal.h @@ -21,6 +21,13 @@ #define ARCH_CPU_INTERNAL_H /* + * Do the necessary work to prepare for secondary CPUs coming up. The + * SoC will call this function before bringing up the other CPUs. The + * entry point for the seoncdary CPUs is returned. + */ +void *prepare_secondary_cpu_startup(void); + +/* * Code path for the non-BSP CPUs. This is an internal function used. */ void arch_secondary_cpu_init(void); diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 8a8e3b6c91..a5d20c49ac 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -97,19 +97,6 @@ int arch_run_on_all_cpus(struct cpu_action *action); int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); int arch_run_on_all_cpus_async(struct cpu_action *action); -/* - * Do the necessary work to prepare for secondary CPUs coming up. The - * SoC will call this function before bringing up the other CPUs. The - * entry point for the seoncdary CPUs is returned. - */ -void *prepare_secondary_cpu_startup(void); - -/* - * Function provided by the SoC code that is called for each secondary - * CPU startup. - */ -void soc_secondary_cpu_init(void); - #endif /* !__PRE_RAM__ */ /* |