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| author | Ronald G. Minnich <rminnich@gmail.com> | 2018-12-19 17:52:43 -0800 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2019-01-17 04:59:09 +0000 |
| commit | 05358047290b5e60cf3c0dc7e967267a03d5c4ce (patch) | |
| tree | ed4340b82c8fa9ae78bf7b8095aa1ad952ef8202 /src/arch | |
| parent | cc394d4d37533a4977c1da629c8ebf405a91d32a (diff) | |
| download | coreboot-05358047290b5e60cf3c0dc7e967267a03d5c4ce.tar.xz | |
riscv: create Kconfig architecture features for new parts
RISCV parts can be created with any one of four CPU modes enabled,
with or without PMP, and with either 32 or 64 bit XLEN.
In anticipation of parts to come, create the Kconfig variables for these
architecture attributes.
Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30348
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/riscv/Kconfig | 38 | ||||
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 19 |
2 files changed, 53 insertions, 4 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9fa43bc9f2..5bde804ce2 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -11,6 +11,44 @@ config RISCV_ABI config RISCV_CODEMODEL string +config ARCH_RISCV_M_DISABLED + bool + +config ARCH_RISCV_M + # Whether a SOC implements M mode. + # M mode is the most privileged mode, it is + # the equivalent in some ways of x86 SMM mode + # save that in M mode it is impossible to turn + # on paging. + # While the spec requires it, there is at least + # one implementation that will not have it due + # to security concerns. + bool + default n if ARCH_RISCV_M_DISABLED + default y + +config ARCH_RISCV_S + # S (supervisor) mode is for kernels. It is optional. + bool + default n + +config ARCH_RISCV_U + # U (user) mode is for programs. + bool + default n + +config ARCH_RISCV_RV64 + bool + default n + +config ARCH_RISCV_RV32 + bool + default n + +config ARCH_RISCV_PMP + bool + default n + config ARCH_BOOTBLOCK_RISCV bool default n diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index aee4b3b167..e4c8468ef0 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -26,10 +26,21 @@ check-ramstage-overlap-regions += stack endif riscv_flags = -I$(src)/arch/riscv/ + +ifeq ($(CONFIG_ARCH_RISCV_RV64),y) +_rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 +else +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +_rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32 +else +$(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32") +endif +endif + ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) else -riscv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 +riscv_flags += $(_rv_flags) endif riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) @@ -56,7 +67,7 @@ bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += smp.c bootblock-y += misc.c -bootblock-y += pmp.c +bootblock-$(ARCH_RISCV_PMP) += pmp.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -85,7 +96,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c romstage-y += stages.c romstage-y += misc.c -romstage-y += pmp.c +romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -127,7 +138,7 @@ ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += payload.S -ramstage-y += pmp.c +ramstage-$(ARCH_RISCV_PMP) += pmp.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ |