This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

37 files changed, 205 insertions, 205 deletions

diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb
index 68b4310248..6a851a5cb7 100644
--- a/src/arch/i386/Config.lb
+++ b/src/arch/i386/Config.lb
@@ -2,14 +2,14 @@ uses CONFIG_CBFS
 uses CONFIG_SMP
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_INIT
-uses HAVE_FAILOVER_BOOT
-uses USE_FAILOVER_IMAGE
-uses USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_USE_FALLBACK_IMAGE
 
 init init/crt0.S.lb
 
 if CONFIG_CBFS
-	if USE_FAILOVER_IMAGE
+	if CONFIG_USE_FAILOVER_IMAGE
 	else
 		initobject /src/lib/cbfs.o
 		initobject /src/console/vsprintf.o
@@ -17,8 +17,8 @@ if CONFIG_CBFS
 	end
 end
 
-if HAVE_FAILOVER_BOOT
-	if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
 		ldscript init/ldscript_failover.lb
 	else
 		if CONFIG_CBFS
@@ -29,13 +29,13 @@ if HAVE_FAILOVER_BOOT
 	end
 else
 	if CONFIG_CBFS
-		if USE_FALLBACK_IMAGE
+		if CONFIG_USE_FALLBACK_IMAGE
 			ldscript init/ldscript_fallback_cbfs.lb
 		else
 			ldscript init/ldscript_cbfs.lb
 		end
 	else
-		if USE_FALLBACK_IMAGE
+		if CONFIG_USE_FALLBACK_IMAGE
 			ldscript init/ldscript_fallback.lb
 		else
 			ldscript init/ldscript.lb
@@ -54,7 +54,7 @@ end
 
 makerule nrv2b 
 	depends	"$(TOP)/util/nrv2b/nrv2b.c"
-	action	"$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
+	action	"$(CONFIG_HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
 end
 
 makerule payload
@@ -91,7 +91,7 @@ if CONFIG_PRECOMPRESSED_PAYLOAD
 	makedefine PAYLOAD-1:=payload
 end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 	makedefine COREBOOT_APC:=
 	makedefine COREBOOT_RAM_ROM:=
 
@@ -102,13 +102,13 @@ if USE_FAILOVER_IMAGE
 else
 	makerule coreboot.rom 
 		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
+		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
 		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi"
 	end
 end
 
 makerule crt0.S
-	depends "$(CRT0)"
+	depends "$(CONFIG_CRT0)"
 	action  "cp $< $@"
 end
 
@@ -118,13 +118,13 @@ if CONFIG_USE_INIT
 	makerule init.o
         	depends "$(INIT-OBJECTS)"
 	        action  "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
-	        action  "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
+	        action  "$(CONFIG_OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
 	end
 
         makerule coreboot   
 		depends	"crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
 		action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
-		action	"$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
+		action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
         end
 
 end
diff --git a/src/arch/i386/boot/Config.lb b/src/arch/i386/boot/Config.lb
index 4b22010461..9c576921a0 100644
--- a/src/arch/i386/boot/Config.lb
+++ b/src/arch/i386/boot/Config.lb
@@ -1,7 +1,7 @@
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_MULTIBOOT
-uses HAVE_ACPI_RESUME
+uses CONFIG_HAVE_ACPI_RESUME
 
 object boot.o
 object coreboot_table.o
@@ -9,13 +9,13 @@ if CONFIG_MULTIBOOT
 object multiboot.o
 end
 object tables.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 object pirq_routing.o 
 end
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 object acpi.o
 object acpigen.o
-if HAVE_ACPI_RESUME
+if CONFIG_HAVE_ACPI_RESUME
 object wakeup.S
 end
 end
diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c
index 658c1b32d8..c0c57190ad 100644
--- a/src/arch/i386/boot/acpi.c
+++ b/src/arch/i386/boot/acpi.c
@@ -390,18 +390,18 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt)
 	rsdp->ext_checksum	= acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
 }
 
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 void suspend_resume(void)
 {
 	void *wake_vec;
 
 #if 0
-#if MEM_TRAIN_SEQ != 0
-	#error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
+#if CONFIG_MEM_TRAIN_SEQ != 0
+	#error "So far it works on AMD and CONFIG_MEM_TRAIN_SEQ == 0"
 #endif
 
-#if _RAMBASE < 0x1F00000
-	#error "For ACPI RESUME you need to have _RAMBASE at least 31MB"
+#if CONFIG_RAMBASE < 0x1F00000
+	#error "For ACPI RESUME you need to have CONFIG_RAMBASE at least 31MB"
 	#error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
 	#error "And coreboot memory reserved in mainboard.c"
 #endif
diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c
index 431ff368cd..659ab0f90e 100644
--- a/src/arch/i386/boot/coreboot_table.c
+++ b/src/arch/i386/boot/coreboot_table.c
@@ -76,15 +76,15 @@ struct lb_memory *lb_memory(struct lb_header *header)
 
 struct lb_serial *lb_serial(struct lb_header *header)
 {
-#if defined(TTYS0_BASE)
+#if defined(CONFIG_TTYS0_BASE)
 	struct lb_record *rec;
 	struct lb_serial *serial;
 	rec = lb_new_record(header);
 	serial = (struct lb_serial *)rec;
 	serial->tag = LB_TAG_SERIAL;
 	serial->size = sizeof(*serial);
-	serial->ioport = TTYS0_BASE;
-	serial->baud = TTYS0_BAUD;
+	serial->ioport = CONFIG_TTYS0_BASE;
+	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
 #else
 	return header;
@@ -157,9 +157,9 @@ struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 
 	cmos_checksum->size = (sizeof(*cmos_checksum));
 
-	cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
-	cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
-	cmos_checksum->location = LB_CKS_LOC * 8;
+	cmos_checksum->range_start = CONFIG_LB_CKS_RANGE_START * 8;
+	cmos_checksum->range_end = ( CONFIG_LB_CKS_RANGE_END * 8 ) + 7;
+	cmos_checksum->location = CONFIG_LB_CKS_LOC * 8;
 	cmos_checksum->type = CHECKSUM_PCBIOS;
 	
 	return cmos_checksum;
@@ -413,7 +413,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
 	return mem;
 }
 
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
@@ -424,7 +424,7 @@ unsigned long write_coreboot_table(
 	struct lb_header *head;
 	struct lb_memory *mem;
 
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 	printk_debug("Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
@@ -460,7 +460,7 @@ unsigned long write_coreboot_table(
 	rom_table_end &= ~0xffff;
 	printk_debug("0x%08lx \n", rom_table_end);
 
-#if (HAVE_OPTION_TABLE == 1) 
+#if (CONFIG_HAVE_OPTION_TABLE == 1) 
 	{
 		struct lb_record *rec_dest, *rec_src;
 		/* Write the option config table... */
@@ -482,13 +482,13 @@ unsigned long write_coreboot_table(
 	lb_add_memory_range(mem, LB_MEM_TABLE, 
 		rom_table_start, rom_table_end-rom_table_start);
 
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 	printk_debug("Adding high table area\n");
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		high_tables_base, high_tables_size);
 #endif
 
-#if (HAVE_MAINBOARD_RESOURCES == 1)
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
 	add_mainboard_resources(mem);
 #endif
 
diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c
index 598cc3ca8d..0c470082e0 100644
--- a/src/arch/i386/boot/pirq_routing.c
+++ b/src/arch/i386/boot/pirq_routing.c
@@ -3,7 +3,7 @@
 #include <string.h>
 #include <device/pci.h>
 
-#if (DEBUG==1 && HAVE_PIRQ_TABLE==1)
+#if (CONFIG_DEBUG==1 && CONFIG_HAVE_PIRQ_TABLE==1)
 static void check_pirq_routing_table(struct irq_routing_table *rt)
 {
 	uint8_t *addr = (uint8_t *)rt;
@@ -12,7 +12,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
 
 	printk_info("Checking Interrupt Routing Table consistency...\n");
 
-#if defined(IRQ_SLOT_COUNT)
+#if defined(CONFIG_IRQ_SLOT_COUNT)
 	if (sizeof(struct irq_routing_table) != rt->size) {
 		printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
 			       sizeof(struct irq_routing_table),
@@ -83,7 +83,7 @@ static int verify_copy_pirq_routing_table(unsigned long addr)
 #define verify_copy_pirq_routing_table(addr)
 #endif
 
-#if HAVE_PIRQ_TABLE==1
+#if CONFIG_HAVE_PIRQ_TABLE==1
 unsigned long copy_pirq_routing_table(unsigned long addr)
 {
 	/* Align the table to be 16 byte aligned. */
@@ -100,7 +100,7 @@ unsigned long copy_pirq_routing_table(unsigned long addr)
 }
 #endif
 
-#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1)
 void pirq_routing_irqs(unsigned long addr)
 {
 	int i, j, k, num_entries;
diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c
index 2dbfa7adcc..9991415eda 100644
--- a/src/arch/i386/boot/tables.c
+++ b/src/arch/i386/boot/tables.c
@@ -104,7 +104,7 @@ struct lb_memory *write_tables(void)
 	post_code(0x9a);
 
 	/* Write ACPI tables to F segment and high tables area */
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
 	if (high_tables_base) {
 		unsigned long acpi_start = high_table_end;
 		rom_table_end = ALIGN(rom_table_end, 16);
@@ -129,7 +129,7 @@ struct lb_memory *write_tables(void)
 #endif
 	post_code(0x9b);
 
-#if HAVE_MP_TABLE == 1
+#if CONFIG_HAVE_MP_TABLE == 1
 	/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
 	rom_table_end = write_smp_table(rom_table_end);
 	rom_table_end = ALIGN(rom_table_end, 1024);
@@ -139,7 +139,7 @@ struct lb_memory *write_tables(void)
 		high_table_end = write_smp_table(high_table_end);
 		high_table_end = ALIGN(high_table_end, 1024);
 	}
-#endif /* HAVE_MP_TABLE */
+#endif /* CONFIG_HAVE_MP_TABLE */
 
 	post_code(0x9c);
 
diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h
index c2ed67971e..5b5797fcd1 100644
--- a/src/arch/i386/include/arch/acpi.h
+++ b/src/arch/i386/include/arch/acpi.h
@@ -13,11 +13,11 @@
 #ifndef __ASM_ACPI_H
 #define __ASM_ACPI_H
 
-#if HAVE_ACPI_TABLES==1
+#if CONFIG_HAVE_ACPI_TABLES==1
 
 #include <stdint.h>
  
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
 /* 0 = S0, 1 = S1 ...*/
 extern u8 acpi_slp_type;
 #endif
@@ -88,13 +88,13 @@ typedef struct acpi_table_header         /* ACPI common table header */
 /* RSDT */
 typedef struct acpi_rsdt {
 	struct acpi_table_header header;
-	u32 entry[7+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
+	u32 entry[7+CONFIG_ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
 } __attribute__ ((packed)) acpi_rsdt_t;
 
 /* XSDT */
 typedef struct acpi_xsdt {
 	struct acpi_table_header header;
-	u64 entry[6+ACPI_SSDTX_NUM];
+	u64 entry[6+CONFIG_ACPI_SSDTX_NUM];
 } __attribute__ ((packed)) acpi_xsdt_t;
 
 /* HPET TIMERS */
@@ -367,7 +367,7 @@ void acpi_create_facs(acpi_facs_t *facs);
 void acpi_write_rsdt(acpi_rsdt_t *rsdt);
 void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt);
 
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
 void suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
 void *acpi_get_wakeup_rsdp(void);
@@ -390,7 +390,7 @@ do {                                                    \
 
 #define IO_APIC_ADDR	0xfec00000UL
 
-#else // HAVE_ACPI_TABLES
+#else // CONFIG_HAVE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
 
diff --git a/src/arch/i386/include/arch/cpu.h b/src/arch/i386/include/arch/cpu.h
index ebe6ed155c..f49b7cb50a 100644
--- a/src/arch/i386/include/arch/cpu.h
+++ b/src/arch/i386/include/arch/cpu.h
@@ -128,8 +128,8 @@ static inline struct cpu_info *cpu_info(void)
 	__asm__("andl %%esp,%0; "
 		"orl  %2, %0 "
 		:"=r" (ci) 
-		: "0" (~(STACK_SIZE - 1)), 
-		"r" (STACK_SIZE - sizeof(struct cpu_info))
+		: "0" (~(CONFIG_STACK_SIZE - 1)), 
+		"r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info))
 	);
 	return ci;
 }
diff --git a/src/arch/i386/include/arch/pci_ops.h b/src/arch/i386/include/arch/pci_ops.h
index 04b93196aa..9c4e029b24 100644
--- a/src/arch/i386/include/arch/pci_ops.h
+++ b/src/arch/i386/include/arch/pci_ops.h
@@ -4,7 +4,7 @@
 extern const struct pci_bus_operations pci_cf8_conf1;
 extern const struct pci_bus_operations pci_cf8_conf2;
 
-#if MMCONF_SUPPORT==1
+#if CONFIG_MMCONF_SUPPORT==1
 extern const struct pci_bus_operations pci_ops_mmconf;
 #endif
 
diff --git a/src/arch/i386/include/arch/pciconf.h b/src/arch/i386/include/arch/pciconf.h
index 5887522c8b..09133b5567 100644
--- a/src/arch/i386/include/arch/pciconf.h
+++ b/src/arch/i386/include/arch/pciconf.h
@@ -5,7 +5,7 @@
 #define	PCI_CONF_REG_INDEX	0xcf8
 #define	PCI_CONF_REG_DATA	0xcfc
 
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
 #else
 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) )
diff --git a/src/arch/i386/include/arch/pirq_routing.h b/src/arch/i386/include/arch/pirq_routing.h
index d3d61a282d..15c616b442 100644
--- a/src/arch/i386/include/arch/pirq_routing.h
+++ b/src/arch/i386/include/arch/pirq_routing.h
@@ -16,8 +16,8 @@ struct irq_info {
 	uint8_t rfu;
 } __attribute__((packed));
 
-#if defined(IRQ_SLOT_COUNT)
-#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
+#if defined(CONFIG_IRQ_SLOT_COUNT)
+#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
 #elif (__GNUC__ < 3)
 #define IRQ_SLOTS_COUNT 1
 #else
@@ -39,10 +39,10 @@ struct irq_routing_table {
 
 extern const struct irq_routing_table intel_irq_routing_table;
 
-#if HAVE_PIRQ_TABLE==1
+#if CONFIG_HAVE_PIRQ_TABLE==1
 unsigned long copy_pirq_routing_table(unsigned long start);
 unsigned long write_pirq_routing_table(unsigned long start);
-#if PIRQ_ROUTE==1
+#if CONFIG_PIRQ_ROUTE==1
 void pirq_routing_irqs(unsigned long start);
 void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
 #else
diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h
index aaba32ab01..fca27c4ec6 100644
--- a/src/arch/i386/include/arch/romcc_io.h
+++ b/src/arch/i386/include/arch/romcc_io.h
@@ -34,7 +34,7 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
 	*((volatile uint32_t *)(addr)) = value;
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 
 #include <arch/mmio_conf.h>
 
@@ -92,7 +92,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha
 static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
 	addr = (dev>>4) | where;
 #else
 	addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
@@ -101,17 +101,17 @@ static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_
 	return inb(0xCFC + (addr & 3));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         return read8x(addr);
 }
 #endif
 static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	return pci_mmio_read_config8(dev, where);
 #else
 	return pci_io_read_config8(dev, where);
@@ -121,7 +121,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d
 static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -130,18 +130,18 @@ static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(devic
 	return inw(0xCFC + (addr & 2));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         return read16x(addr);
 }
 #endif
 
 static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	return pci_mmio_read_config16(dev, where);
 #else
         return pci_io_read_config16(dev, where);
@@ -152,7 +152,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t
 static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -161,18 +161,18 @@ static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(devic
 	return inl(0xCFC);
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         return read32x(addr);
 }
 #endif
 
 static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	return pci_mmio_read_config32(dev, where);
 #else
         return pci_io_read_config32(dev, where);
@@ -182,7 +182,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t
 static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -191,18 +191,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config8(device_t
 	outb(value, 0xCFC + (addr & 3));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         write8x(addr, value);
 }
 #endif
 
 static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	pci_mmio_write_config8(dev, where, value);
 #else
         pci_io_write_config8(dev, where, value);
@@ -213,7 +213,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev
 static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -222,18 +222,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config16(device_t
         outw(value, 0xCFC + (addr & 2));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         write16x(addr, value);
 }
 #endif
 
 static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	pci_mmio_write_config16(dev, where, value);
 #else
 	pci_io_write_config16(dev, where, value);
@@ -244,7 +244,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de
 static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -253,18 +253,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config32(device_t
 	outl(value, 0xCFC);
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         write32x(addr, value);
 }
 #endif
 
 static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	pci_mmio_write_config32(dev, where, value);
 #else
         pci_io_write_config32(dev, where, value);
@@ -286,7 +286,7 @@ static device_t pci_io_locate_device(unsigned pci_id, device_t dev)
 
 static device_t pci_locate_device(unsigned pci_id, device_t dev)
 {
-	for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
+	for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
 		unsigned int id;
 		id = pci_read_config32(dev, 0);
 		if (id == pci_id) {
diff --git a/src/arch/i386/init/car.S b/src/arch/i386/init/car.S
index 94ffc648c5..98e40ad0cf 100644
--- a/src/arch/i386/init/car.S
+++ b/src/arch/i386/init/car.S
@@ -72,8 +72,8 @@ __protected_stage0:
  * the other is very similar to the AMD CAR, except remove amd specific msr
  */
 
-#define CacheSize DCACHE_RAM_SIZE
-#define CacheBase DCACHE_RAM_BASE
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
+#define CacheBase CONFIG_DCACHE_RAM_BASE
 
 #include <cpu/x86/mtrr.h>
 
@@ -241,14 +241,14 @@ clear_fixed_var_mtrr_out:
 	 */
 	movl    $0x202, %ecx
 	xorl    %edx, %edx
-	movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl    $0x203, %ecx
 	movl    $0x0000000f, %edx
-	movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
 	/* enable cache */
 	movl    %cr0, %eax
diff --git a/src/arch/i386/init/crt0.S.lb b/src/arch/i386/init/crt0.S.lb
index cf7c2ab5e9..e60144840c 100644
--- a/src/arch/i386/init/crt0.S.lb
+++ b/src/arch/i386/init/crt0.S.lb
@@ -37,14 +37,14 @@
 
 #include "crt0_includes.h"
 
-#if USE_DCACHE_RAM == 0
+#if CONFIG_USE_DCACHE_RAM == 0
 #ifndef CONSOLE_DEBUG_TX_STRING
 	/* uses:	 esp, ebx, ax, dx */
 # define __CRT_CONSOLE_TX_STRING(string) \
 	mov	string, %ebx	; \
 	CALLSP(crt_console_tx_string)
 
-# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 #  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
 # else
 #  define CONSOLE_DEBUG_TX_STRING(string)
@@ -102,26 +102,26 @@ crt_console_tx_string:
 	RETSP
 9:
 /* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE	0x3f8
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE	0x3f8
 #endif
 /* Data */
-#define TTYS0_RBR (TTYS0_BASE+0x00)
+#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
 
 /* Control */
 #define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (TTYS0_BASE+0x01)
-#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
+#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
 #define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (TTYS0_BASE+0x03)
-#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
+#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
 #define TTYS0_DLL TTYS0_RBR
 #define TTYS0_DLM TTYS0_IER
 
 /* Status */
-#define TTYS0_LSR (TTYS0_BASE+0x05)
-#define TTYS0_MSR (TTYS0_BASE+0x06)
-#define TTYS0_SCR (TTYS0_BASE+0x07)
+#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
+#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
+#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
 	
 	mov	%al, %ah
 10:	mov	$TTYS0_LSR, %dx
@@ -143,7 +143,7 @@ str_copying_to_ram:  .string "Uncompressing coreboot to RAM.\r\n"
 str_copying_to_ram:  .string "Copying coreboot to RAM.\r\n"
 #endif
 #if CONFIG_CBFS
-# if USE_FALLBACK_IMAGE == 1
+# if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
 # else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
@@ -154,4 +154,4 @@ str_pre_main:        .string "Jumping to coreboot.\r\n"
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
 
-#endif /* USE_DCACHE_RAM */
+#endif /* CONFIG_USE_DCACHE_RAM */
diff --git a/src/arch/i386/init/ldscript.lb b/src/arch/i386/init/ldscript.lb
index 50a8c9965d..0ed5c47f53 100644
--- a/src/arch/i386/init/ldscript.lb
+++ b/src/arch/i386/init/ldscript.lb
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -35,7 +35,7 @@ TARGET(binary)
 INPUT(coreboot_ram.rom)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	.ram . : {
 		_ram = . ;
@@ -56,7 +56,7 @@ SECTIONS
 
 	_lrom = LOADADDR(.rom);
 	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;
diff --git a/src/arch/i386/init/ldscript_apc.lb b/src/arch/i386/init/ldscript_apc.lb
index ce491547b0..2c8cb84e63 100644
--- a/src/arch/i386/init/ldscript_apc.lb
+++ b/src/arch/i386/init/ldscript_apc.lb
@@ -6,7 +6,7 @@ SECTIONS
                 coreboot_apc.rom(*)
                 _eapcrom = .;
         }
-        _iseg_apc = DCACHE_RAM_BASE;
+        _iseg_apc = CONFIG_DCACHE_RAM_BASE;
         _eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
         _liseg_apc = _apcrom;
         _eliseg_apc = _eapcrom;
diff --git a/src/arch/i386/init/ldscript_cbfs.lb b/src/arch/i386/init/ldscript_cbfs.lb
index e86befb1ca..37e867db21 100644
--- a/src/arch/i386/init/ldscript_cbfs.lb
+++ b/src/arch/i386/init/ldscript_cbfs.lb
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -34,7 +34,7 @@ ENTRY(_start)
 TARGET(binary)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/* This section might be better named .setup */
 	.rom . : {
diff --git a/src/arch/i386/init/ldscript_failover.lb b/src/arch/i386/init/ldscript_failover.lb
index 064f159a50..099cae9d8a 100644
--- a/src/arch/i386/init/ldscript_failover.lb
+++ b/src/arch/i386/init/ldscript_failover.lb
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -34,7 +34,7 @@ ENTRY(_start)
 TARGET(binary)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/* This section might be better named .setup */
 	.rom . : {
diff --git a/src/arch/i386/init/ldscript_fallback.lb b/src/arch/i386/init/ldscript_fallback.lb
index a46c374520..6d41cbde87 100644
--- a/src/arch/i386/init/ldscript_fallback.lb
+++ b/src/arch/i386/init/ldscript_fallback.lb
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -35,7 +35,7 @@ TARGET(binary)
 INPUT(coreboot_ram.rom)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	.ram . : {
 		_ram = . ;
@@ -45,7 +45,7 @@ SECTIONS
 
 	/* cut _start into last 64k*/
 	_x = .;
-	. = (_x < (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE) : _x;
+	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
 
 	/* This section might be better named .setup */
 	.rom . : {
@@ -61,7 +61,7 @@ SECTIONS
 
 	_lrom = LOADADDR(.rom);
 	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;
diff --git a/src/arch/i386/init/ldscript_fallback_cbfs.lb b/src/arch/i386/init/ldscript_fallback_cbfs.lb
index 52274d1356..eb3bf3f0d7 100644
--- a/src/arch/i386/init/ldscript_fallback_cbfs.lb
+++ b/src/arch/i386/init/ldscript_fallback_cbfs.lb
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -34,11 +34,11 @@ ENTRY(_start)
 TARGET(binary)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/* cut _start into last 64k*/
 	_x = .;
-	. = (_x < (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE) : _x;
+	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
 
 	/* This section might be better named .setup */
 	.rom . : {
diff --git a/src/arch/i386/lib/Config.lb b/src/arch/i386/lib/Config.lb
index 52da9d5e59..0a07e3b9be 100644
--- a/src/arch/i386/lib/Config.lb
+++ b/src/arch/i386/lib/Config.lb
@@ -1,6 +1,6 @@
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
-uses USE_FAILOVER_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
 uses CONFIG_CBFS
 
 object c_start.S
@@ -13,7 +13,7 @@ object exception.c
 
 initobject printk_init.o
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
 	if CONFIG_CBFS
 		initobject cbfs_and_run.o
diff --git a/src/arch/i386/lib/console_printk.c b/src/arch/i386/lib/console_printk.c
index f4b35a192c..a3c409c5c1 100644
--- a/src/arch/i386/lib/console_printk.c
+++ b/src/arch/i386/lib/console_printk.c
@@ -11,39 +11,39 @@ extern int do_printk(int msg_level, const char *fmt, ...);
 #define printk_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
 #define printk_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
 
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
 #undef  printk_emerg
 #define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
 #undef  printk_alert
 #define printk_alert(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
 #undef  printk_crit
 #define printk_crit(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
 #undef  printk_err
 #define printk_err(fmt, arg...)     do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
 #undef  printk_warning
 #define printk_warning(fmt, arg...) do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
 #undef  printk_notice
 #define printk_notice(fmt, arg...)  do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
 #undef  printk_info
 #define printk_info(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
 #undef  printk_debug
 #define printk_debug(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
 #undef  printk_spew
 #define printk_spew(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
diff --git a/src/arch/i386/lib/failover_failover.lds b/src/arch/i386/lib/failover_failover.lds
index 814f2000fb..ec8c12a9e4 100644
--- a/src/arch/i386/lib/failover_failover.lds
+++ b/src/arch/i386/lib/failover_failover.lds
@@ -1,2 +1,2 @@
 	__fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
-	__normal_image = ((CONFIG_ROM_PAYLOAD_START - FALLBACK_SIZE) & 0xfffffff0) - 8;
+	__normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;
diff --git a/src/arch/i386/lib/id.inc b/src/arch/i386/lib/id.inc
index 46b4424511..c2f634ea00 100644
--- a/src/arch/i386/lib/id.inc
+++ b/src/arch/i386/lib/id.inc
@@ -3,12 +3,12 @@
 	.globl __id_start
 __id_start:
 vendor:	
-	.asciz MAINBOARD_VENDOR
+	.asciz CONFIG_MAINBOARD_VENDOR
 part:		
-	.asciz MAINBOARD_PART_NUMBER
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x10 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x10 - part    /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
diff --git a/src/arch/i386/lib/id.lds b/src/arch/i386/lib/id.lds
index ccdf7008f7..8f9149a6a1 100644
--- a/src/arch/i386/lib/id.lds
+++ b/src/arch/i386/lib/id.lds
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
diff --git a/src/arch/i386/lib/pci_ops_conf1.c b/src/arch/i386/lib/pci_ops_conf1.c
index 4c4cd672e6..36db54c21b 100644
--- a/src/arch/i386/lib/pci_ops_conf1.c
+++ b/src/arch/i386/lib/pci_ops_conf1.c
@@ -8,7 +8,7 @@
  * Functions for accessing PCI configuration space with type 1 accesses
  */
 
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
 #define CONFIG_CMD(bus,devfn, where)   (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
 #else
 #define CONFIG_CMD(bus,devfn, where)   (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )
diff --git a/src/arch/i386/lib/pci_ops_mmconf.c b/src/arch/i386/lib/pci_ops_mmconf.c
index c037a7b4cd..a6057084f0 100644
--- a/src/arch/i386/lib/pci_ops_mmconf.c
+++ b/src/arch/i386/lib/pci_ops_mmconf.c
@@ -1,4 +1,4 @@
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 
 #include <console/console.h>
 #include <arch/io.h>
@@ -13,7 +13,7 @@
  */
 
 #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \
-	MMCONF_BASE_ADDRESS | \
+	CONFIG_MMCONF_BASE_ADDRESS | \
         (((SEGBUS) & 0xFFF) << 20) | \
         (((DEVFN) & 0xFF) << 12) | \
         ((WHERE) & 0xFFF))
diff --git a/src/arch/i386/lib/printk_init.c b/src/arch/i386/lib/printk_init.c
index 7c03664a4f..4b26930580 100644
--- a/src/arch/i386/lib/printk_init.c
+++ b/src/arch/i386/lib/printk_init.c
@@ -14,7 +14,7 @@
 /* Keep together for sysctl support */
 /* Using an global varible can cause problem when we reset the stack from cache as ram to ram*/
 #if 0
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 #else
 #define console_loglevel ASM_CONSOLE_LOGLEVEL
 #endif
@@ -25,8 +25,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char);
 void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')
-		uart8250_tx_byte(TTYS0_BASE, '\r');
-	uart8250_tx_byte(TTYS0_BASE, byte);
+		uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
+	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
 }
 
 int do_printk(int msg_level, const char *fmt, ...)
diff --git a/src/arch/i386/smp/Config.lb b/src/arch/i386/smp/Config.lb
index b41f5c295e..18aa70ac86 100644
--- a/src/arch/i386/smp/Config.lb
+++ b/src/arch/i386/smp/Config.lb
@@ -1,6 +1,6 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 
-if HAVE_MP_TABLE
+if CONFIG_HAVE_MP_TABLE
   object mpspec.o 
 end
 #object ioapic.o CONFIG_IOAPIC
diff --git a/src/arch/ppc/boot/coreboot_table.c b/src/arch/ppc/boot/coreboot_table.c
index b1420a7491..dc154b2a71 100644
--- a/src/arch/ppc/boot/coreboot_table.c
+++ b/src/arch/ppc/boot/coreboot_table.c
@@ -340,7 +340,7 @@ unsigned long write_coreboot_table(
 
 	head = lb_table_init(low_table_end);
 	low_table_end = (unsigned long)head;
-	if (HAVE_OPTION_TABLE == 1) {
+	if (CONFIG_HAVE_OPTION_TABLE == 1) {
 		struct lb_record *rec_dest, *rec_src;
 		/* Write the option config table... */
 		rec_dest = lb_new_record(head);
diff --git a/src/arch/ppc/include/arch/cpu.h b/src/arch/ppc/include/arch/cpu.h
index e0ed4ff66a..3026486420 100644
--- a/src/arch/ppc/include/arch/cpu.h
+++ b/src/arch/ppc/include/arch/cpu.h
@@ -13,24 +13,24 @@ struct cpu_driver {
 	struct cpu_device_id *id_table;
 };
 
-#ifndef STACK_SIZE
-#error STACK_SIZE not defined
+#ifndef CONFIG_STACK_SIZE
+#error CONFIG_STACK_SIZE not defined
 #endif
 
 /* The basic logic comes from the Linux kernel.
- * The invariant is that (1 << 31 - STACK_BITS) == STACK_SIZE
+ * The invariant is that (1 << 31 - STACK_BITS) == CONFIG_STACK_SIZE
  * I wish there was simpler way to support multiple stack sizes.
  * Oh well.
  */
-#if STACK_SIZE == 4096
+#if CONFIG_STACK_SIZE == 4096
 #define STACK_BITS "19"
-#elif STACK_SIZE == 8192
+#elif CONFIG_STACK_SIZE == 8192
 #define STACK_BITS "18"
-#elif STACK_SIZE == 16384
+#elif CONFIG_STACK_SIZE == 16384
 #define STACK_BITS "17"
-#elif STACK_SIZE == 32768
+#elif CONFIG_STACK_SIZE == 32768
 #define STACK_BITS "16"
-#elif STACK_SIZE == 65536
+#elif CONFIG_STACK_SIZE == 65536
 #define STACK_BITS "15"
 #else
 #error Unimplemented stack size
diff --git a/src/arch/ppc/include/arch/io.h b/src/arch/ppc/include/arch/io.h
index fd0d1e4654..ba8ce4fa85 100644
--- a/src/arch/ppc/include/arch/io.h
+++ b/src/arch/ppc/include/arch/io.h
@@ -11,8 +11,8 @@
 
 #define SLOW_DOWN_IO
 
-#ifndef _IO_BASE
-#define _IO_BASE	0
+#ifndef CONFIG_IO_BASE
+#define CONFIG_IO_BASE	0
 #endif
 
 #define readb(addr) in_8((volatile uint8_t *)(addr))
@@ -36,15 +36,15 @@
  * are arrays of bytes, and byte-swapping is not appropriate in
  * that case.  - paulus
  */
-#define insw(port, buf, ns)	_insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw(port, buf, ns)	_outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns)	_insw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)	_outsw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
 
-#define inb(port)		in_8((uint8_t *)((port)+_IO_BASE))
-#define outb(val, port)		out_8((uint8_t *)((port)+_IO_BASE), (val))
-#define inw(port)		in_le16((uint16_t *)((port)+_IO_BASE))
-#define outw(val, port)		out_le16((uint16_t *)((port)+_IO_BASE), (val))
-#define inl(port)		in_le32((uint32_t *)((port)+_IO_BASE))
-#define outl(val, port)		out_le32((uint32_t *)((port)+_IO_BASE), (val))
+#define inb(port)		in_8((uint8_t *)((port)+CONFIG_IO_BASE))
+#define outb(val, port)		out_8((uint8_t *)((port)+CONFIG_IO_BASE), (val))
+#define inw(port)		in_le16((uint16_t *)((port)+CONFIG_IO_BASE))
+#define outw(val, port)		out_le16((uint16_t *)((port)+CONFIG_IO_BASE), (val))
+#define inl(port)		in_le32((uint32_t *)((port)+CONFIG_IO_BASE))
+#define outl(val, port)		out_le32((uint32_t *)((port)+CONFIG_IO_BASE), (val))
 
 #define inb_p(port)		inb((port))
 #define outb_p(val, port)	outb((val), (port))
@@ -56,8 +56,8 @@
 /*
  * The *_ns versions below do byte-swapping.
  */
-#define insw_ns(port, buf, ns)	_insw((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw_ns(port, buf, ns)	_outsw((uint16_t *)((port)+_IO_BASE), (buf), (ns))
+#define insw_ns(port, buf, ns)	_insw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns)	_outsw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
 
 
 #define IO_SPACE_LIMIT ~0
diff --git a/src/arch/ppc/include/arch/pirq_routing.h b/src/arch/ppc/include/arch/pirq_routing.h
index dad8531eb5..00c9556319 100644
--- a/src/arch/ppc/include/arch/pirq_routing.h
+++ b/src/arch/ppc/include/arch/pirq_routing.h
@@ -16,8 +16,8 @@ struct irq_info {
 	u8 rfu;
 } __attribute__((packed));
 
-#if defined(IRQ_SLOT_COUNT)
-#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
+#if defined(CONFIG_IRQ_SLOT_COUNT)
+#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
 #elif (__GNUC__ < 3)
 #define IRQ_SLOTS_COUNT 1
 #else
@@ -39,13 +39,13 @@ struct irq_routing_table {
 
 extern const struct irq_routing_table intel_irq_routing_table;
 
-#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
+#if defined(CONFIG_DEBUG) && defined(CONFIG_HAVE_PIRQ_TABLE)
 void check_pirq_routing_table(void);
 #else
 #define check_pirq_routing_table() do {} while(0)
 #endif
 
-#if defined(HAVE_PIRQ_TABLE)
+#if defined(CONFIG_HAVE_PIRQ_TABLE)
 unsigned long copy_pirq_routing_table(unsigned long start);
 #else
 #define copy_pirq_routing_table(start) (start)
diff --git a/src/arch/ppc/init/crt0.S.lb b/src/arch/ppc/init/crt0.S.lb
index 738d4b4a67..bbccc59213 100644
--- a/src/arch/ppc/init/crt0.S.lb
+++ b/src/arch/ppc/init/crt0.S.lb
@@ -30,8 +30,8 @@ system_reset:
 	 */
 %%PROCESSOR_INIT%%
 
-#if USE_DCACHE_RAM == 1
-#define DCACHE_RAM_END	(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
+#if CONFIG_USE_DCACHE_RAM == 1
+#define DCACHE_RAM_END	(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
 	/*
 	 * Initialize data cache blocks 
 	 * (assumes cache block size of 32 bytes)
@@ -39,9 +39,9 @@ system_reset:
 	 * NOTE: This may need to be moved to FAMILY_INIT if
 	 *       dcbz is not supported on all CPU's
 	 */
-	lis     r1, DCACHE_RAM_BASE@h
-	ori     r1, r1, DCACHE_RAM_BASE@l
-	li      r3, (DCACHE_RAM_SIZE / 32)
+	lis     r1, CONFIG_DCACHE_RAM_BASE@h
+	ori     r1, r1, CONFIG_DCACHE_RAM_BASE@l
+	li      r3, (CONFIG_DCACHE_RAM_SIZE / 32)
 	mtctr   r3
 0:      dcbz    r0, r1
 	addi    r1, r1, 32
@@ -53,8 +53,8 @@ system_reset:
 	 * it 16-byte aligned to cover both cases. Also we have to ensure that
 	 * the first word is located within the cache.
 	 */
-	lis     r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h
-	ori     r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l
+	lis     r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
+	ori     r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
 	lis	r0, 0
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
@@ -65,8 +65,8 @@ system_reset:
 	/*
 	 * Clear stack
 	 */
-	lis	r4, DCACHE_RAM_BASE@h
-	ori	r4, r4, DCACHE_RAM_BASE@l
+	lis	r4, CONFIG_DCACHE_RAM_BASE@h
+	ori	r4, r4, CONFIG_DCACHE_RAM_BASE@l
 	lis	r7, DCACHE_RAM_END@h
 	ori	r7, r7, DCACHE_RAM_END@l
 	lis	r5, 0
@@ -110,7 +110,7 @@ system_reset:
 	 * Complete rest of initialization in C (ppc_main)
 	 */
 	rfi
-#endif /* USE_DCACHE_RAM */
+#endif /* CONFIG_USE_DCACHE_RAM */
 
 	/*
 	 * Stop here if something goes wrong
diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb
index a81d9b9bb8..453c99c13b 100644
--- a/src/arch/ppc/init/ldscript.lb
+++ b/src/arch/ppc/init/ldscript.lb
@@ -1,14 +1,14 @@
 /*
  *	Memory map:
  *
- *	_ROMBASE		: start of ROM
- *	_RESET			: reset vector (may be at top of ROM)
+ *	CONFIG_ROMBASE		: start of ROM
+ *	CONFIG_RESET			: reset vector (may be at top of ROM)
  *	_EXCEPTIONS_VECTORS	: exception table
  *
- *	_ROMSTART 		: coreboot text 
+ *	CONFIG_ROMSTART 		: coreboot text 
  *				: payload text
  *
- *	_RAMBASE		: address to copy payload
+ *	CONFIG_RAMBASE		: address to copy payload
  */
 
 /*
@@ -32,13 +32,13 @@ SECTIONS
 	/* 
 	 * Absolute location of base of ROM 
 	 */
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/*
 	 * Absolute location of reset vector. This may actually be at the
 	 * the top of ROM.
 	 */
-	. = _RESET;
+	. = CONFIG_RESET;
 	.reset . : {
 		*(.rom.reset);
 		. = ALIGN(16);
@@ -47,7 +47,7 @@ SECTIONS
 	/*
 	 * Absolute location of exception vector table.
 	 */
-	. = _EXCEPTION_VECTORS;
+	. = CONFIG_EXCEPTION_VECTORS;
 	.exception_vectors . : {
 		*(.rom.exception_vectors);
 		. = ALIGN(16);
@@ -56,7 +56,7 @@ SECTIONS
 	/*
 	 * Absolute location of coreboot initialization code in ROM.
 	 */
-	. = _ROMSTART;
+	. = CONFIG_ROMSTART;
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
@@ -94,7 +94,7 @@ SECTIONS
 	/*
 	 * Absolute location of where coreboot will be relocated in RAM.
 	 */
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;
diff --git a/src/arch/ppc/lib/pci_dev.c b/src/arch/ppc/lib/pci_dev.c
index adb047e3fe..d821f17c77 100644
--- a/src/arch/ppc/lib/pci_dev.c
+++ b/src/arch/ppc/lib/pci_dev.c
@@ -9,8 +9,8 @@ uint8_t pci_ppc_read_config8(unsigned char bus, int devfn, int where)
 {
 	uint8_t res;
 
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	res = in_8((unsigned char *)PCIC0_CFGDATA + (where & 3));
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	res = in_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3));
 	return res;
 }
 
@@ -18,8 +18,8 @@ uint16_t pci_ppc_read_config16(unsigned char bus, int devfn, int where)
 {
 	uint16_t res;
 
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	res = in_le16((unsigned short *)PCIC0_CFGDATA + (where & 2));
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	res = in_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2));
 	return res;
 }
 
@@ -27,28 +27,28 @@ uint32_t pci_ppc_read_config32(unsigned char bus, int devfn, int where)
 {
 	uint32_t res;
 
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	res = in_le32((unsigned *)PCIC0_CFGDATA);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	res = in_le32((unsigned *)CONFIG_PCIC0_CFGDATA);
 	return res;
 }
 
 int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data)
 {
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	out_8((unsigned char *)PCIC0_CFGDATA + (where & 3), data);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	out_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3), data);
 	return 0;
 }
 
 int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data)
 {
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	out_le16((unsigned short *)PCIC0_CFGDATA + (where & 2), data);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	out_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2), data);
 	return 0;
 }
 
 int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data)
 {
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	out_le32((unsigned *)PCIC0_CFGDATA, data);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	out_le32((unsigned *)CONFIG_PCIC0_CFGDATA, data);
 	return 0;
 }
diff --git a/src/arch/ppc/lib/printk_init.c b/src/arch/ppc/lib/printk_init.c
index 401d271391..98d78b3fc4 100644
--- a/src/arch/ppc/lib/printk_init.c
+++ b/src/arch/ppc/lib/printk_init.c
@@ -12,7 +12,7 @@
 
 /* Keep together for sysctl support */
 
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 
 extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
 extern void uart8250_tx_byte(unsigned, unsigned char);
@@ -20,8 +20,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char);
 void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')
-		uart8250_tx_byte(TTYS0_BASE, '\r');
-	uart8250_tx_byte(TTYS0_BASE, byte);
+		uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
+	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
 }
 
 int do_printk(int msg_level, const char *fmt, ...)