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authorDavid Hendricks <dhendrix@chromium.org>2013-03-25 19:50:11 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-03-26 21:10:46 +0100
commit42f5513d3d09e50eee6279c401897f34b1eb0053 (patch)
treef62bb532954a61eeb2a3ccfdbdfa665acc0e472f /src/arch
parent49675b950f2cbd40455dd1584ae8dfb50a1f3274 (diff)
downloadcoreboot-42f5513d3d09e50eee6279c401897f34b1eb0053.tar.xz
armv7: fixes for dcache_op_by_mva()
This fixes a couple issues with dcache_op_by_mva(): - Add missing data and instruction sync barriers. - Removes unneded -1 from loop terminating condition. Change-Id: I098388614397c1e53079c017d56b1cf3ef273676 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2913 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/armv7/lib/cache.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index 2686db7cf9..c93da36e7c 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -183,7 +183,9 @@ static void dcache_op_mva(unsigned long addr,
unsigned long line, i;
line = line_bytes();
- for (i = addr & ~(line - 1); i < addr + len - 1; i += line) {
+
+ dsb();
+ for (i = addr & ~(line - 1); i < addr + len; i += line) {
switch(op) {
case OP_DCCIMVAC:
dccimvac(addr);
@@ -192,6 +194,7 @@ static void dcache_op_mva(unsigned long addr,
break;
}
}
+ isb();
}
void dcache_clean_by_mva(unsigned long addr, unsigned long len)