arch/x86: Make postcar TempRamExit call generic

Move the FSP-specific call for tearing down cache-as-RAM out of
postcar.c and replace it with an empty weak function.

This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)).  The
temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built
when CONFIG_FSP_CAR is true.

Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 15 insertions, 4 deletions

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 8a44ef96c0..4327abed55 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -297,6 +297,13 @@ void *postcar_commit_mtrrs(struct postcar_frame *pcf);
  * utilizes prog_run() internally.
  */
 void run_postcar_phase(struct postcar_frame *pcf);
+
+/*
+ * Systems without a native coreboot cache-as-ram teardown may implement
+ * this to use an alternate method.
+ */
+void late_car_teardown(void);
+
 #endif
 
 #endif /* ARCH_CPU_H */
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
index 34a4335121..7b5be6e9f0 100644
--- a/src/arch/x86/postcar.c
+++ b/src/arch/x86/postcar.c
@@ -13,18 +13,22 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <main_decl.h>
 #include <program_loading.h>
 #include <soc/intel/common/util.h>
-#include <fsp/util.h>
+
+/*
+ * Systems without a native coreboot cache-as-ram teardown may implement
+ * this to use an alternate method.
+ */
+__attribute__((weak)) void late_car_teardown(void) { /* do nothing */ }
 
 void main(void)
 {
-	/* Call TempRamExit FSP API if enabled. */
-	if (IS_ENABLED(CONFIG_FSP_CAR))
-		fsp_temp_ram_exit();
+	late_car_teardown();
 
 	console_init();