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authorDavid Hendricks <dhendrix@chromium.org>2013-04-30 12:20:53 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-05-01 08:17:01 +0200
commitc99ae5d9a93212cbecff0d10a1710b68f26e966e (patch)
treebda50cfde94896974430f741ec4e256e0ee13941 /src/arch
parent0004c0deec8d60cf952426746e2d9519f6de38d6 (diff)
downloadcoreboot-c99ae5d9a93212cbecff0d10a1710b68f26e966e.tar.xz
armv7: add wrapper for tlbimvaa
This adds an inline wrapper for the TLBIMVAA instruction (invalidate unified TLB by MVA, all address space identifiers). Change-Id: Ibcd289ecedaba8586ade26e36c177ff1fcaf91d3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3161 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/armv7/include/arch/cache.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 1db86dc57c..028cf1808d 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -108,6 +108,12 @@ static inline void tlbiall(void)
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
}
+/* invalidate unified TLB by MVA, all ASID */
+static inline void tlbimvaa(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
+}
+
/* write data access control register (DACR) */
static inline void write_dacr(uint32_t val)
{