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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-28 19:52:05 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-18 19:47:01 +0100 |
| commit | 7b22d84d55386ee422fa77c1d8bce9dddeaaa231 (patch) | |
| tree | 7c1afd131b1c3a504bae653cffb3e87d5062dac0 /src/arch | |
| parent | 5a3f1e54d55b416361d486d3b9136c65b6847242 (diff) | |
| download | coreboot-7b22d84d55386ee422fa77c1d8bce9dddeaaa231.tar.xz | |
drivers/pc80: Add optional spinlock for nvram CBFS access
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following:
AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030]
Decoding the faulting address:
0x000000fdf9103300
fdf91x Hypertransport system management region
33 SysMgtCmd (System Management Command) = 0x33
3 Base Command Type = 0x3: STPCLK (Stop Clock request)
3 SMAF (System Management Action Field) = [3:1] = 0x1
1 Signal State Bit Map = [0] = 0x1
Therefore, the error appears to be triggered by an upstream C1E request.
This was eventually traced to concurrent access to the SP5100's SPI Flash controller by
multiple APs during startup. Calls to the nvram read functions get_option and read_option
call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash
controller, thus placing the SP5100 in an invalid state. This limitation is not documented
in any public AMD errata, and was only discovered through considerable debugging effort.
Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/include/arch/smp/spinlock.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 74e532c68a..057d9e3f8f 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) +#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -14,6 +14,8 @@ typedef struct { #ifdef __PRE_RAM__ spinlock_t *romstage_console_lock(void); void initialize_romstage_console_lock(void); +spinlock_t* romstage_nvram_cbfs_lock(void); +void initialize_romstage_nvram_cbfs_lock(void); #endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } |