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| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-08 16:22:10 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 20:16:25 +0200 |
| commit | 7b5f8ef2eab7f1211888ae420d76176f49721601 (patch) | |
| tree | 82ad463c16b6f2e12499e606ae9e27a507fffd7b /src/arch | |
| parent | fb370130f6618d53f506566737f7394ee1417c55 (diff) | |
| download | coreboot-7b5f8ef2eab7f1211888ae420d76176f49721601.tar.xz | |
arch: Fix spelling
Change-Id: Ifea10f0180c0c4b684030a168402a95fadf1a9db
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3727
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/armv7/include/armv7.h | 2 | ||||
| -rw-r--r-- | src/arch/armv7/include/assembler.h | 2 | ||||
| -rw-r--r-- | src/arch/x86/boot/acpi.c | 4 | ||||
| -rw-r--r-- | src/arch/x86/boot/tables.c | 2 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/armv7/include/armv7.h b/src/arch/armv7/include/armv7.h index dc111c17ee..147323457a 100644 --- a/src/arch/armv7/include/armv7.h +++ b/src/arch/armv7/include/armv7.h @@ -59,7 +59,7 @@ /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 - * However, we use the CP15 based instructtions because we use + * However, we use the CP15 based instructions because we use * -march=armv5 in U-Boot */ #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h index 5e4789b145..7acf0f4a9a 100644 --- a/src/arch/armv7/include/assembler.h +++ b/src/arch/armv7/include/assembler.h @@ -55,6 +55,6 @@ #endif /* - * Cache alligned + * Cache aligned */ #define CALGN(code...) code diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 3b77caa314..96cb270814 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -248,7 +248,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) } /* - * This can be overriden by platform ACPI setup code, if it calls + * This can be overridden by platform ACPI setup code, if it calls * acpi_create_ssdt_generator(). */ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator( @@ -763,7 +763,7 @@ void acpi_jump_to_wakeup(void *vector) #endif #if CONFIG_SMP - // FIXME: This should go into the ACPI backup memory, too. No pork saussages. + // FIXME: This should go into the ACPI backup memory, too. No pork sausages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 6355a1b9dc..3cc2c6b041 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -66,7 +66,7 @@ struct lb_memory *write_tables(void) rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyound 0x400. Only multiboot, GDT + * in case our data structures grow beyond 0x400. Only multiboot, GDT * and the coreboot table use low_tables. */ low_table_start = 0; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 7363132a19..6944834169 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -8,7 +8,7 @@ */ #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ -#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */ #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ |