diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-09-09 14:37:03 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-14 01:43:57 +0200 |
| commit | 8f993784ef71f451995dd67fc709b88399c8a7e9 (patch) | |
| tree | d2cbe6361bb6e1c9dcc4ead2273cc66007a06ceb /src/arch | |
| parent | fa938c7508627c0dfcf03960957ef8631fc53f02 (diff) | |
| download | coreboot-8f993784ef71f451995dd67fc709b88399c8a7e9.tar.xz | |
ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM
Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix@chromium.org>
Tested-by: David Hendrix <dhendrix@chromium.org>
(cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/armv7/ramstage.ld | 13 | ||||
| -rw-r--r-- | src/arch/armv7/romstage.ld | 2 |
2 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/armv7/ramstage.ld b/src/arch/armv7/ramstage.ld index 42090f4610..91efe2c4d0 100644 --- a/src/arch/armv7/ramstage.ld +++ b/src/arch/armv7/ramstage.ld @@ -1,7 +1,7 @@ /* * Memory map: * - * CONFIG_RAMBASE : text segment + * CONFIG_RAMSTAGE_BASE : text segment * : rodata segment * : data segment * : bss segment @@ -31,7 +31,7 @@ PHDRS SECTIONS { - . = CONFIG_SYS_SDRAM_BASE; + . = CONFIG_RAMSTAGE_BASE; /* First we place the code and read only data (typically const declared). * This could theoretically be placed in rom. */ @@ -111,9 +111,6 @@ SECTIONS } _eheap = .; - _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; - /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on * the fly, but including stack and heap. @@ -121,6 +118,12 @@ SECTIONS _ram_seg = _text; _eram_seg = _eheap; + /* The stack lives in SRAM in a different location, so keep + * it out of ram_seg + */ + _stack = CONFIG_STACK_BOTTOM; + _estack = CONFIG_STACK_TOP; + /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0203efb135..0ebcd53bae 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -1,7 +1,7 @@ /* * Memory map: * - * CONFIG_RAMBASE : text segment + * CONFIG_ROMSTAGE_BASE : text segment * : rodata segment * : data segment * : bss segment |