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author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-11 13:04:14 -0700 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-12 17:09:59 +0100 |
commit | d4bc0679540842d78712b41707c2da9f3d7ae204 (patch) | |
tree | 30ef0888bd8fec4b86759769bf7bad5477376baf /src/arch | |
parent | 215f27856399b1e4cfe30268fad61bf821af3c19 (diff) | |
download | coreboot-d4bc0679540842d78712b41707c2da9f3d7ae204.tar.xz |
SPI: Add early romstage SPI driver using hardware sequencing
This is a basic romstage driver that can be used for the
MRC cache code on systems where we do not have the MRC cache
stored in a flash region that is memory mapped.
It uses the hardware sequencing interface to avoid having
to know anything about the flash chip itself.
BUG=chrome-os-partner:15031
BRANCH=stout
TEST=manual: this was tested with debug code added to romstage
that attempted to read the MRC cache at offset 0x3e0000.
SPI READ offset=003e0000 size=64 buffer=ff7fba00
SPI ADDR 0x003e0000
SPI HSFC 0x3f00
SPI READ: 0=4443524d
SPI READ: 1=00000bb0
SPI READ: 2=00008e24
SPI READ: 3=00000000
SPI READ: 4=001c8bbb
SPI READ: 5=0c206466
SPI READ: 6=0a043220
SPI READ: 7=000058b4
SPI READ: 8=00000000
SPI READ: 9=00000000
SPI READ: 10=00100000
SPI READ: 11=00100005
SPI READ: 12=20202025
SPI READ: 13=000e0001
SPI READ: 14=00000000
SPI READ: 15=00000000
Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1777
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions