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| author | Hung-Te Lin <hungte@chromium.org> | 2013-08-06 20:37:55 +0800 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-07-31 18:31:53 +0200 |
| commit | 0682cfefdb888807bef6ee7f3bb81615282e0390 (patch) | |
| tree | ebf77bbb06c2c326d0aa3ab7e0390069d8118cb5 /src/arch | |
| parent | c3fda416a7e71eae4803c07f0fae4b0b931d1ca8 (diff) | |
| download | coreboot-0682cfefdb888807bef6ee7f3bb81615282e0390.tar.xz | |
armv7/exynos5420: Configure CPU cores for kernel to enable SMP.
The SMP on Exynos 5420 requires setting a special page and entry wrappers in
firmware side (SRAM) so kernel can start cores (and to switch clusters).
Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64770
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6405
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/armv7/include/arch/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h index 2613025348..ec37a969ce 100644 --- a/src/arch/armv7/include/arch/cpu.h +++ b/src/arch/armv7/include/arch/cpu.h @@ -98,4 +98,10 @@ inline static void sev(void) asm volatile ("sev"); } +/* puts CPU into SVC32 mode and disable interrupts. */ +inline static void set_svc32_mode(void) +{ + asm volatile("msr cpsr_c, %0" :: "r"(0x13 | 0xc0)); +} + #endif /* __ARCH_CPU_H__ */ |