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| author | Yen Lin <yelin@nvidia.com> | 2014-10-29 17:42:47 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-09 14:40:14 +0200 |
| commit | db3f383494053535e3f0e19ea1346c8084ee54eb (patch) | |
| tree | 800f02b2c315bbc39ce1792ad7138a104321cdac /src/arch | |
| parent | b777f3e3d1cb4265f1a4bf392781b93bd0c37eea (diff) | |
| download | coreboot-db3f383494053535e3f0e19ea1346c8084ee54eb.tar.xz | |
tegra132: configure debug uart to 115200n8 in tegra_lp0_resume
Need to configure debug uart port to have proper baudrate/width/parity.
Hard-code it to 115200n8.
BUG=chrome-os-partner:32015
BRANCH=None
TEST=successfully suspend/resume on Rush/Ryu
Change-Id: I502fd8361baf2bea642fabbc4d5e126da5411ba3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c70625ad41efca9117c8682113b226e929e93c5
Original-Change-Id: I6a96c80654ce52f5b877fd46995ca8c1aceb7017
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226407
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9391
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions