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| author | Julius Werner <jwerner@chromium.org> | 2019-03-07 17:07:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-25 11:03:49 +0000 |
| commit | 5d1f9a009647c741e8587015b14f1e852e1c489e (patch) | |
| tree | b6e87bac2f8a578b7bee6b73111e04bd3750eeb8 /src/arch | |
| parent | 2de19038beffa154eefe40755b607aa9f94d9f9f (diff) | |
| download | coreboot-5d1f9a009647c741e8587015b14f1e852e1c489e.tar.xz | |
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/armv7/mmu.c | 4 | ||||
| -rw-r--r-- | src/arch/x86/failover.ld | 6 | ||||
| -rw-r--r-- | src/arch/x86/memlayout.ld | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 14f5f7ade9..ce9d3fd9d8 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -277,7 +277,7 @@ void mmu_init(void) for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES) table[0] = ATTR_UNUSED; - if (CONFIG_ARM_LPAE) { + if (CONFIG(ARM_LPAE)) { pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB); pte_t *pmd = ttb_buff; int i; @@ -331,7 +331,7 @@ void mmu_init(void) * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. */ write_ttbcr( - CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */ + CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */ 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ ); diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29bef..a9a5942a2f 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -28,7 +28,7 @@ SECTIONS * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -50,10 +50,10 @@ SECTIONS * address gets applied. */ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0); /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), + _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 8e073f25cf..cc72552254 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -26,7 +26,7 @@ SECTIONS * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, (CONFIG_RELOCATABLE_RAMSTAGE ? 8M : + RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M : CONFIG_RAMTOP - CONFIG_RAMBASE)) #elif ENV_ROMSTAGE |