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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-05 07:56:38 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-04-07 02:31:36 +0000
commitd2cdfff63b6e2376fad729252a57acfd2b4418ea (patch)
tree01d0ccd1e0826c9449a6c4f1781e7feb813fe537 /src/arch
parentbf0970e762a6611cef06af761bc2dec068d439bb (diff)
downloadcoreboot-d2cdfff63b6e2376fad729252a57acfd2b4418ea.tar.xz
device/pci: Rewrite PCI MMCONF with symbol reference
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/include/arch/pci_mmio_cfg_romcc.h72
-rw-r--r--src/arch/x86/include/arch/pci_ops.h6
2 files changed, 78 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
new file mode 100644
index 0000000000..00e8e41088
--- /dev/null
+++ b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PCI_MMIO_CFG_ROMCC_H
+#define _PCI_MMIO_CFG_ROMCC_H
+
+#include <stdint.h>
+#include <device/mmio.h>
+#include <device/pci_type.h>
+
+
+static __always_inline
+uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
+{
+ void *addr;
+ addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
+ return read8(addr);
+}
+
+static __always_inline
+uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
+{
+ void *addr;
+ addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
+ return read16(addr);
+}
+
+static __always_inline
+uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
+{
+ void *addr;
+ addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
+ return read32(addr);
+}
+
+static __always_inline
+void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
+{
+ void *addr;
+ addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
+ write8(addr, value);
+}
+
+static __always_inline
+void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
+{
+ void *addr;
+ addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
+ write16(addr, value);
+}
+
+static __always_inline
+void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
+{
+ void *addr;
+ addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
+ write32(addr, value);
+}
+
+#endif /* _PCI_MMIO_CFG_ROMCC_H */
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index e706216586..4278ed0dfd 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -15,6 +15,12 @@
#define ARCH_I386_PCI_OPS_H
#include <arch/pci_io_cfg.h>
+
+#if defined(__ROMCC__)
+/* Must come before <device/pci_mmio_cfg.h> */
+#include <arch/pci_mmio_cfg_romcc.h>
+#endif
+
#include <device/pci_mmio_cfg.h>
#endif /* ARCH_I386_PCI_OPS_H */