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authorSam Lewis <sam.vr.lewis@gmail.com>2020-07-05 19:52:18 +1000
committerJulius Werner <jwerner@chromium.org>2020-07-07 21:48:30 +0000
commite69b1af925e489930f7b441840c7d8b9cb71be62 (patch)
treeb67a2ceb11c09194aaeb51120e4411a9c0dcbfdd /src/arch
parent93d7bcbc67658fd1fb2ec084666283eb4b5dc728 (diff)
downloadcoreboot-e69b1af925e489930f7b441840c7d8b9cb71be62.tar.xz
armv7: mmu: Use 'tlbimva' to invalidate TLB entries
The tlbimvaa operation (invalidate unified TLB by MVA, all address space identifiers) is only available on armv7 processors that support Multiprocessing Extensions. When used on processors that do not support the extensions it causes an "undefined instruction" exception. This patch changes the MMU table entry filling code to use the tlbimva (invalidate unified TLB entry by MVA and address space identifier) operation for invalidating TLB entries, which is supported on all armv7 processors. As address space identifiers are not used in TLB entries in coreboot (all entries are set as global), these two operations can safely be used interchangeably. The ASID value supplied to the operation is not checked for global TLB entries. More information as well as the data formats for the tlbimvaa and tlbimva operations are detailed in the "ARM Architecture Reference Manual ARMv7-A" edition, issue "C.c" page B4-1747. TEST: Booted Beaglebone Black (my current in progress port) Change-Id: Ie7dfb4adab20dc7eecb1b20aa2ee6355215a1521 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/armv7/mmu.c4
-rw-r--r--src/arch/arm/include/armv7/arch/cache.h6
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index d823c61f35..51b4860768 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -118,7 +118,7 @@ static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx,
/* Invalidate the TLB entries. */
for (i = start_idx; i < end_idx; i++)
- tlbimvaa(offset + (i << shift));
+ tlbimva(offset + (i << shift));
dsb();
isb();
}
@@ -152,7 +152,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry)
*pgd_entry = (pte_t)(uintptr_t)table | ATTR_NEXTLEVEL;
dccmvac((uintptr_t)pgd_entry);
dsb();
- tlbimvaa(start_addr);
+ tlbimva(start_addr);
dsb();
isb();
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index 600ec46f91..e332c31663 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -73,10 +73,10 @@ static inline void tlbiall(void)
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
}
-/* invalidate unified TLB by MVA, all ASID */
-static inline void tlbimvaa(unsigned long mva)
+/* invalidate unified TLB by MVA and ASID */
+static inline void tlbimva(unsigned long mva)
{
- asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
+ asm volatile ("mcr p15, 0, %0, c8, c7, 1" : : "r" (mva) : "memory");
}
/* write data access control register (DACR) */